STMicroelectronics STM32F429 - User Manual

September 2013 DocID023833 Rev 5 1/36
STM32F42xx and STM32F43xx
Errata sheet
STM32F427/437 and STM32F429/439 line limitations
Silicon identification
This errata sheet applies to the revision A and Y of STMicroelectronics STM32F427/437
and STM32F429/439 microcontroller lines.
The STM32F42xx and STM32F43xx devices feature an ARM
®
32-bit Cortex™-M4 core with
FPU, for which an errata notice is also available (see Section 1 for details).
The full list of part numbers is shown in Table 2. The products are identifiable as shown in
Table 1:
• by the revision code marked below the order code on the device package
• by the last three digits of the Internal order code printed on the box label
Table 1. Device identification
(1)
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0090
STM32F4xx reference manual for details on how to find the revision code).
Order code Revision code marked on device
(2)
2. Refer to Appendix A: Revision code on device marking for details on how to identify the revision code and
the date code on the different packages.
STM32F427xx, STM32F429xx
“A” and “Y”
STM32F437xx, STM32F439xx
Table 2. Device summary
Reference Part number
STM32F427xx
STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427VI, STM32F427ZI,
STM32F427II
STM32F437xx
STM32F437VG, STM32F437ZG, STM32F437IG, STM32F437VI, STM32F437ZI,
STM32F437II
STM32F429xx
STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429VI, STM32F429ZI,
STM32F429II, STM32F429BG, STM32F429BI, STM32F429NI, STM32F429NG
STM32F439xx
STM32F439VI, STM32F439VG, STM32F439ZG, STM32F439ZI, STM32F439IG,
STM32F439II, STM32F439BG, STM32F439BI, STM32F439NI, STM32F439NG
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STMicroelectronics STM32F429 Specifications

General

Series	STM32F4
Core Size	32-Bit
Maximum Clock Frequency	180MHz
DAC Channels	2
Timers	17
UART	6
Oscillator Type	Internal, External
Core Processor	ARM Cortex-M4
ADC Resolution	12 bit
DAC Resolution	12 bit
Connectivity	CAN, Ethernet, I2C, SPI, UART
Peripherals	DMA, LCD
Operating Temperature	-40°C ~ 85°C
Package / Case	LQFP

Summary

ARM 32-bit Cortex-M4 with FPU Limitations

Cortex-M4 Interrupted Loads to Stack Pointer

Interrupt during SP load can cause erroneous behavior; instruction executes an extra time.

STM32 F42 xx;STM32 F43 xx System Limitations

Clocking Delays and ADC Accuracy

Covers RCC clock enabling delays and internal noise impacting ADC accuracy.

Ethernet Peripheral Limitations

FMC Peripheral Limitations

SDRAM Bank Access and Data Corruption

Covers read access to non-initialized SDRAM banks and FMC data read corruption.

Burst Interruption and Async Access Conflicts

Covers CPU burst read interruption and NOR/PSRAM async access conflicts.

SDIO Peripheral Limitations

Clock Dephasing, Busy Signal, and Underrun Detection

Covers clock dephasing data corruption, busy signal management, and underrun detection.

ADC and DAC Peripheral Limitations

ADC Sequencer Modification During Conversion

Modifying ADC registers during software-started conversion resets it; no auto-restart.