Supermicro X10SRL-F - Page 78

4-10
X10SRL-F User’s Manual
Chipset Conguration
North Bridge
This feature allows the user to congure the settings for the Intel North Bridge.
IIO Conguration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
IIO1 Conguration
CPU SLOT3 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT4 PCI-E 3.0 X8 (IN X16)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT5 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT6 PCI-E 3.0 X8 (IN X16)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT7 PCI-E 3.0 X8
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
IOAT Conguration
Enable I/OAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology), which signi-
cantly reduces CPU overhead by leveraging CPU architectural improvements
and freeing the system resource for other tasks. The options are Enable and
Disable.