49
Chapter 2: Installation
SMBus Header
Pin Denitions
Pin# Denition
1 Data
2 Ground
3 Clock
USB10/11(3.0)
AUDIO FP
PCH SLOT4 PCI-E 3.0 X4(IN X8)
CPU SLOT6 PCI-E 3.0 X16
PCH SLOT7 PCI-E 3.0 X4(IN X8)
DP1/DP2
VGA/DVI
LAN3/4
LAN1/2
USB2/3(3.0)
IPMI_LAN
USB0/1
1
1
1
1
1
1
1
1
1
X11SSZ-F
REV: 1.10
MAC CODE
MAC CODE
MAC CODE
MAC CODE
MAC CODE
BAR CODE
DESIGNED IN USA
BIOS LICENSE
CPU Socket LGA1151
S/N CODE
Intel
C236
1
1
USB8/9
USB6/7
USB4/5
I-SGPIO1
JPW2
SP1
BT1
LED1
LED2
JD1
JBT1
JPI2C1
JGPIO1
FAN4
FAN2
FAN1
FANB
FANA
FAN3
JTPM1
JSPDIF_OUT1
JL1
J18
JI2C2
JI2C1
JPW1
JPME2
JBR2
JBR3
JPL3
JPL2
JPL1
JBR1
JWD1
JPB1
JPG1
JPAC1
COM2
COM1
LED4
LED3
JSD1
J15
DIMMA1
DIMMA2
DIMMB1
DIMMB2
JF1
I-SATA1
I-SATA2
I-SATA3
I-SATA0
JUIDB1
JIPMB1
JSMB1
1
1
1
JVR1
JVRM1
JVRM2
USB12
4
3
2
JPWR1
1
2
1. SMBus Header
2. DOM Power Connector
System Management Bus Header
A System Management Bus header for additional slave devices or sensors is located at
JSMB1. Refer to the table below for pin denitions.
Disk-On-Module Power Connector
The Disk-On-Module (DOM) power connector at JSD1 provides 5V power to a solid-state
DOM storage device connected to one of the SATA ports. Refer to the table below for pin
denitions.
DOM Power
Pin Denitions
Pin# Denition
1 5V
2 Ground
3 Ground
USB10/11(3.0)
AUDIO FP
PCH SLOT4 PCI-E 3.0 X4(IN X8)
CPU SLOT6 PCI-E 3.0 X16
PCH SLOT7 PCI-E 3.0 X4(IN X8)
DP1/DP2
VGA/DVI
LAN3/4
LAN1/2
USB2/3(3.0)
IPMI_LAN
USB0/1
1
1
1
1
1
1
1
1
1
X11SSZ-F
REV: 1.10
MAC CODE
MAC CODE
MAC CODE
MAC CODE
MAC CODE
BAR CODE
DESIGNED IN USA
BIOS LICENSE
CPU Socket LGA1151
S/N CODE
Intel
C236
1
1
USB8/9
USB6/7
USB4/5
I-SGPIO1
JPW2
SP1
BT1
LED1
LED2
JD1
JBT1
JPI2C1
JGPIO1
FAN4
FAN2
FAN1
FANB
FANA
FAN3
JTPM1
JSPDIF_OUT1
JL1
J18
JI2C2
JI2C1
JPW1
JPME2
JBR2
JBR3
JPL3
JPL2
JPL1
JBR1
JWD1
JPB1
JPG1
JPAC1
COM2
COM1
LED4
LED3
JSD1
J15
DIMMA1
DIMMA2
DIMMB1
DIMMB2
JF1
I-SATA1
I-SATA2
I-SATA3
I-SATA0
JUIDB1
JIPMB1
JSMB1
1
1
1
JVR1
JVRM1
JVRM2
USB12
4
3
2
JPWR1
1
3