because the standard allows only for all the DIN polarity to be set at a time.
This guarantees backwards compatibility.
Examples:
Setting polarity for only DIN6 and EIR lines
igpioctrl(id, I_GPIO_T61622_POL, T61622_DIN06 | T61622_EIR)
Reading back the polarity setting
igpiostat(id, I_GPIO_T61622_POL, &pol);
TAMS 61622 Latching
This function allows latching the levels of the lines enabled, in the three different
groups DIN[0..15], STI0, STI1, and EIR lines, in two different fashions
depending on what polarity is set for each line in each group (please refer to
point 3: TAMS 61622 Polarity).
♦ polarity set to 0, the latch will occur on a LO to HI (logically) transition.
♦ polarity set to 1, the latch will occur on a HI to LO (logically) transition.
♦ This function has three different requests:
♦ I_GPIO_T61622_LAT_EN controls which group of lines are enabled for
latching, DIN[0..15], STI0, STI1 and/or EIR.
♦ I_GPIO_T61622_LAT_RD lets you read the latched lines.
♦ I_GPIO_T61622_LAT_CL clears the latched lines.
Examples:
Enable T61622_DIN06 and T61622_EIR
igpioctrl (id, I_GPIO_T61622_LAT_EN, T61622_DIN06 | T61622_EIR)
Read who is enabled for latching
igpiostat(id, I_GPIO_T61622_LAT_EN, &len)
Read latched lines
igpiostat(id, I_GPIO_T61622_LAT_RD, &lat)
Clear latched lines
igpioctrl(id, I_GPIO_T61622_LAT_CL, lat)
TAMS 61622 line interrupt
This function controls which lines can cause an interrupt. Interrupts on level
transitions on DIN[0..15], STI[0..1] and EIR lines can be controlled individually. The
interrupt occurs on LO to HI (logically) transition on a GPIO
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