TCL PDP42U3H - Page 37

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ANALOG GND
ADD
FLI2300
1
PDP42U3H
14 21Monday, June 14, 2004
Title
Size Document Number Rev
Date: Sheet
of
U2
ADDR0
SDA
V0
Y6
BA1
DI_VSYNC_test
Y1
DAC1.8V
U6
ADDR4
U4
BA0
ADDR2
U0
DAC1.8V
SDRAM_CLK
U7
DQM
WEN
ADDR[0..10]
ADDR1 ADDR6 ADDR9
SDRAM_CLKIN
b7C5
Y3
ADDR7 ADDR8
V4
V3
r1C7
U1
Y4
DATA[0..31]
RASN
CSN
V6
Y7
V[0..7]
V5
U5
U[0..7]
SCL
U3
CASN
ADDR10
b6C4
Y0
Y[0..7] V7
Y5
ADDR5
DI_HSYNC_test
ADDR3
Y2
V1
V2
r0C6
R_OUT
G_OUT
B_OUT
DI_HSYNC_test
DI_VSYNC_test
C4
C5
C6
C7
b5C3
b3C1
OE_DIG/MCA1B
r3
r2
b1
b0
r7
r6
r4
r5
DATA23
DATA26
DATA8 DATA9 DATA4
DATA16 DATA19 DATA24 DATA10
DATA5
DATA12
DATA6
DATA17 DATA22 DATA14
DATA29
DATA25
DATA31
DATA7
DATA11 DATA15
DATA1
DATA2
DATA20
DATA27 DATA30
DATA3
DATA0
DATA13 DATA21
DATA28
DATA18
PC1
PC2
PC15
PC14
PC5
PC13
PC11
G/Y2 g2
PC12
PC3
PC4
PC10
G/Y1 g1
PC7
G/Y0 g0
G/Y7 g7
G/Y6 g6
G/Y5 g5
G/Y3 g3
G/Y4 g4
PC6
PC0
PC9
PC8
G/Y6
G/Y4
G/Y7
G/Y5
G/Y0
G/Y1
G/Y3
G/Y2
b2C0
b4C2
C1
C3
C0
C2
b0
b1
b3
b2
b5
b4
b7
b6
r5
r1
r6
r4
r7
r0
r3
r2
g5
g1
g6
g4
g7
g0
g3
g2
PB_g5
PB_g1
PB_g6
PB_g4
PB_g7
PB_g0
PB_g3
PB_g2
PB_r5
PB_r1
PB_r6
PB_r4
PB_r7
PB_r0
PB_r3
PB_r2
PB_b5
PB_b1
PB_b6
PB_b4
PB_b7
PB_b0
PB_b3
PB_b2
AD_VSYNC15
AD_HSYNC15
DU[0..7]15
BA0 13
DQM 13
SDRAM_DATA[0..31] 13
RASN 13
BA1 13
CSN 13
ADDR[0..10] 13
P_CLK15
SDRAM_CLKIN 13
WEN 13
CASN 13
SDRAM_CLK 13
DI_YCLK 10
P_CLK15
SCL_3V4,10,15
SDA_3V4,10,15
MC_SCLK 4
MC_DATA 4
REST5,10
HS_AD_IN15,16
VS_AD_IN15,16
DY[0..7]15
DV[0..7]15
OE_DIG/MCA184
PC[15..0] 10
SOGOUT15
PB_b[7..0] 10
PB_r[7..0] 10
PB_g[7..0] 10
DI_VSYNC 10
DI_HSYNC 10
+1.8V
GND
+1.8VD
GND
GND_ANALOG
+1.8VD
GND
PLL1.8V
GND
DAC3.3V
PGND3
GND
PLL1.8V
GND_ANALOG
GND
DAC3.3V
GND
+3.3V
PGND3
+3.3VD
GND
GND
DAC1.8V
GND
PLL1.8V
+3.3VD
+3.3VD
GND
+3.3V
GND_ANALOG
GND
DAC1.8V+1.8VD
DAC3.3V
+3.3VD
PGND3 GND
GND GND
GND
+5V
GND
RP11 22Rx4
18
27
36
45
R110
0R
+
C144
47UF/16V
RP001 22Rx4
18
27
36
45
RP12 22Rx4
18
27
36
45
C141
.1uF/50V
R109
10K/5%
+
C128
100uF/16V
C142
.1uF/50V
C133
.1uF/50V
C143
.1uF/50V
+
C145
47UF/16V
P3
JST-S4B-PH-K
1
2
3
4
+3.3V
GND
SCL
SDA
C134
.1uF/50V
C147
.1uF/50V
TP3
probe
1
C135
.1uF/50V
C139
.1uF/50V
TP2
probe
1
C148
.1uF/50V
TP4
probe
1
C136
.1uF/50V
C130
.1uF/50V
C123
.1uF/50V
C131
.1uF/50V
C132
.1uF/50V
C149
.1uF/50V
RP003 22Rx4
18
27
36
45
C140
.1uF/50V
+
C146
100uF/16V
+
C120
10UF/16V
s2300
U12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1(3.3)
VSSio
IN_CLK2_PORT1
PORT1_A0
PORT1_A1
PORT1_A2
PORT1_A3
PORT1_A4
VDDcore1(1.8)
VSScore
PORT1_A5
PORT1_A6
PORT1_A7
PORT1_B0
PORT1_B1
PORT1_B2
PORT1_B3
PORT1_B4
PORT1_B5
PORT1_B6
PORT1_B7
PORT1_C0
VDD2(3.3)
VSSio
PORT1_C1
PORT1_C2
PORT1_C3
PORT1_C4
VDDcore2(1.8)
VSScore
PORT1_C5
PORT1_C6
PORT1_C7
IN_SEL
FILM SYNC_IN
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3(3.3)
VSSio
SDRAM DATA0
SDRAM DATA1
SDRM DT2
SDRAM DATA3 SDRAM DATA4 SDRAM DATA5 SDRAM DATA6 SDRAM DATA7 SDRAM DATA8 SDRAM DATA9 SDRAM DATA10 SDRAM DATA11 VDD4(3.3) VSSio SDRAM DATA12 SDRAM DATA13 SDRAM DATA14 SDRAM DATA15 VDDcore3(1.8) VSScore SDRAM DATA16 SDRAM DATA17 SDRAM DATA18 SDRAM DATA19 SDRAM DATA20 SDRAM DATA21 SDRAM DATA22 SDRAM DATA23 SDRAM DATA24 SDRAM DATA25 VDDcore4(1.8) VSScore SDRAM DATA26 SDRAM DATA27 SDRAM DATA28 SDRAM DATA29 SDRAM DATA30 SDRAM DATA31 VDD5(3.3) VSSio TEST IN SDRAM ADDR10 SDRAM ADDR9 SDRAM ADDR8 SDRAM ADDR7 SDRAM ADDR6 VDDcore5(1.8) VSScore SDRAM ADDR5 SDRAM ADDR4 SDRAM ADDR3 SDRAM ADDR2 SDRAM ADDR1 SDRAM ADDR0 WEN
OE
VID_OUT7
VID_OUT6
VID_OUT5
VID_OUT4
VID_OUT3
VID_OUT2
VID_OUT1
VID_OUT0
VSSio
VDD8(3.3)
VID_OUT15
VID_OUT14
VID_OUT13
VID_OUT12
VID_OUT11
VID_OUT10
VSScore
VDDcore7(1.8)
VID_OUT9
VID_OUT8
VID_OUT23
VID_OUT22
VID_OUT21
VID_OUT20
VID_OUT19
VID_OUT18
VSSio
VDD7(3.3)
VID_OUT17
VID_OUT16
CLKOUT
VSScore
VDDcore6(1.8)
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSSio
VDD6(3.3)
SDRAM CLKOUT
DQM
CSN
BA0
BA1
CASN
RASN
HSYN_PORT2
VSYN_PORT2
FILDID_PRT2
PORT2_7 PORT2_6 PORT2_5 PORT2_4 PORT2_3 PORT2_2 PORT2_1
VSScore
VDDcore8(1.8)
PORT2_0
IN_CLK_PORT2
VSSio
VDD9(3.3)
XTAL OUT
XTAL IN
TEST2 TEST1 TEST0
DAC_PVDD(3.3)
DAC_GR_AVDD(3.3)
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD(3.3)
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_AVSSR
DAC_AVDDR(3.3)
DAC_ROUT
DAC_AVSSG
DAC_AVDDG(3.3)
DAC_GOUT
DAC_AVSSB
DAC_AVDDB(3.3)
DAC_BOUT
DAC_VSS
DAC_VDD(1.8)
DAC_PVSS
AVSS_PLL_FE
AVDD_PLL_FE(1.8)
AVDD_PLL_SDI(1.8)
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2(1.8) AVDD_PLL_BE1(1.8)
AVSS_PLL_BE1
PLL_PVSS
PLL_PVDD(1.8)
RP004 22Rx4
18
27
36
45
C150
.1uF/50V
C156
.1uF/50V
RP005 22Rx4
18
27
36
45
C138
.1uF/50V
RP006 22Rx4
18
27
36
45
C154
.1uF/50V
C157
.1uF/50V
R107 0R
OR5 10R
C129
.1uF/50V
C125
.1uF/50V
C158
.1uF/50V
C153
.1uF/50V
R106 0R
D22
LTE-4208
1 2
L21
RFC
C159
.1uF/50V
C152
.1uF/50V
C155
.1uF/50V
R104
187/1%
C151
.1uF/50V
OR21 10R
RP002 22Rx4
18
27
36
45
JP2
HEADER 9
1
2
3
4
5
6
7
8
9
OR4 10R
+
C124
10UF/16V
R305
0
R111 0R
OR3 0
R108 10R
R112 0R
C137
.1uF/50V
12
C121
33pF/5%
12
C119
.1uF/50V
C122
33pF/5%
12
Q19
C1815
L23 5.6uH
+
C126
10UF/16V
R330
1K
R131
4.7K
R113 0R
C381
NC
C127
.1uF/50V
X1
13.5MHz
1 2
3
R285 0
OR22
0
C380
NC
RP7 22Rx4
18
27
36
45
R126 10R
RP8 22Rx4
18
27
36
45
FB003
12
R286 0
R105
47K,5%
OR6 10R
37