EasyManua.ls Logo

Teac MT-20D-IO - Page 39

Teac MT-20D-IO
253 pages
Save Page as PDF
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
In
each
case,
the
RDY(H)
signal
is
set
by
CPU
prior
to
the
transfer
of
each
block.
During
read
operation,
the
HDRQ(H)
signal
is
also
set
simultaneously
(timing
(!)).
During
write
operation,
the
data
from
the
HOST
is
latched
in
the
register
within
this
IC
by
the
leading
edge
of
HDRQ(H),
and
the
data
is
stored
in
RAM
by
the
IOR(L)
and
NW(L)
signals
outputted
from
D¥~C
together
with
HDACK(L).
During
read
operation,
the
beginning
data
request
of
each
block
to
DMAC
is
set
by
CPU
(timing
(!)).
MR(L)
and
IOW(L)
are
outputted
from
DMAC,
and
the
data
is
written
in
the
register
within
this
IC.
In
any
case,
the
data
block
is
transferred
in
512
bytes
units,
and
the
RDY
signal
is
set
by
CPU
prior
to
the
transfer
of
each
block
(timing
(!)).
When
end
data
of
each
block
is
transferred,
the
EOP(L)
signal
is
outputted
from
DMAC
together
with
the
HDACK(L)
signal,
and
Fly
within
this
IC
is
set
(timing
~),
and
thereby
the
CPU
identifies
the
transfer
of
one
block
to
be
ended.
- 327 -

Related product manuals