Teac MT-20D-IO - Page 43

CPU
BUS
'---
.---
WRITE
GCR
SHIFT
DATA
MPX
f----
CONVER-
f--
REG.
REG.
TER
Lr
~
CRC
GENERATOR
READ
GCR
SHIFT
DATA
CONVER-
-
REG.
REG.
TER
CRC CHECKER ~
READ
CLOCK
VFO
Fig. 319 Write/read control lpgic block diagram
- 331 -
I--
(
CMT SIDE
WO
WRITE DATA)
RO
(READ DATA)