Teac MT-20D-IO - Page 42

3-4-7 Write/read control
The hardware of the write/read control consists of a gate array logic
(U14/IC, W/R control) and VFO circuit.
Fig. 319 shows the block diagram of the write/read control including the
internal logic of this IC.
(1) Write control logic
The write data is transferred byte by byte from RAM by DMAC. The
write control logic converts this data into GCR code in 4 bits units
while generating a CRC character, and further converts the resultant
code into serial data in phase with the write clock to be outputted
to CMT.
The CRC character generated is outputted in the same format in
succession to the end data of one block.
(2) Read control logic
The read clock in phase with the serial Read Data (RD) outputted from
CMT is generated in the VFO circuit. The serial Read Data (RD) is
sampled by this read clock, and parallel GCR code is set up in the
shift register. This code is subj ected to GCR reverse conversion,
and the resultant code is inputted to the CRC checker and at the same
time, it is transferred byte by byte to RAM under the control of
DMAC.
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