Teac MT-20D-IO - Page 57

3-5-6 Counter/timer
The counter/timer consists of timers within an IC 82CS4(US) and IC 81CSS-
(U4).
The timer within IC 81CSS divides the frequency of the CPU clock to generate
the clock of 50 kHz.
Among the three counters within Ie 82CS4. the counter 0 (the output from Pin
No. 10) generates the write clock (TP3) by dividing the frequency of the
3.6 MHz clock. and supplies the resultant write clock to the write control
logic (U9/2309).
The counter 1 receives the above-mentioned 50 kHz clock as the input, and
uses it as a timer for monitoring the various times.
The counter 2 receives the encoder pulses (J4-12) outputted from CMT as the
input. and controls the tape position by counting these pulses.
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