Teac MT-20D-IO - Page 56

3-5-5 D}f..AC
The DMAC consists of an IC 82C37 DMA controller (U8) and 8-bit address
latch.
The channel 0 is assigned with host interface control, and the channel 1
with write control. and then the channel 2 with read control.
During write/read operation. the relevant two channels are always operated
simultaneously. With the 30 ips model. during write operation, the channel
2 is also operated only for the beginning 4 bytes of each block on the tape
in read after write operation.
Namely, the three channels are operated simultaneously only in such a case.
BLKDET ITP I)
RDACK III rrn
EOPILl U
Fig. 325 Channel 2 timing in write operation (30 ips)
Note that the I/O system and memory system of the write/read signal of DMAC
are connected reversely to those of CPU as shown in Table 302 below.
Table 302 Write/read signal corresponding table
CPU bus signal name 82C37 signal
name
MW(L)
lOW
MR(L)
IOR
-
10W(L)
MW
-
IOR(L) MR
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