Teac PD-135 - Page 22

VEE FEO Fe. FE+ TWC TOO TDt-TO1+ TH
IC & TRANSISTOR LEAD IDENTIFICATION
HM6116 BLOCK DIAGRAM
Ad (4)
AS (3)
AG (2)
A7 U1}
AS (23)
AY (22)
AtG(19)
16384B1T
(128 « 128)
MEMORY CELL ARRAY
1/01 49)
(14)
13)
1708 01)
AO At
(a) (7)
A2 AS
(6) (5)
TS sy
WE t21)
SE (20)
XC488AO0O BLOCK DIAGRAM
Focus Drive Amp
FRE Comparator Focus Error Amp
Tracking Control Switch
Tracking Drive Limiter
T& TS TOF CTH TER TPO TP1 TE E Fr
YM3015 BLOCK DIAGRAM
CLOCK SMP! SMP2
O-?
sD SHIFT REGISTER TIMING
LATCH
ORM eee
SELECT FORM
PRIORITY Tos
DETECT Eau 17
Le
TEL) 10 Le DAC
RBG
BC
PEO vCOXx yCoI po ‘TESTA. TESTO, TESTC
O OO 4 ——— «a
TESTO. TEL
EMI O SLICE CLOCK
EFMX, EFRT O CONTROL OSCILLATION
Seto arro QO sus , vFSY
sveoO Seto arro Ea Orc
me Oe © Ea SERVO
QOIN
a On
Orew
Fcs© ae ae Eas INTERFACE Ova
FIC, FRF O im
OK
KP-,
TROF . TRGL. TD O oe ees
HETERO SERVO CONTRO ite
row rorreoe Of a _ as
Sed
Ck ,DATA,OSY CE UE es
ae
ao-a10O ie RAM_ADRESS eh c1,¢2 OFLS
€.40 |__| Cont ROL ERROR
DETECTION
AND:
spre OATA: CONTROL’ EDRREE TION
PLOCESSING
MP2
DIGITAL O84, SAMP! SAI
GAC OUTPUT OQ aouT , oS NC
Quer
~23-