Technics SL-PJ27 - Page 18

SL-PJ27
e 1C301 (MN6625): Digital signal processor
0
Ro | et | tn | Paton
p+ | amor | 0 Serial data byte clock
(Not used, open)
Crystal frame clock (7.35kHz)
a — Ea ANS es eran)
De-emphasis ON signal
(de-emphasis ON at “H”)
+ [ome [0 [emonea nae oot
Ps [se [0 [ewer oacnen
re [are [0 [insist
[woe [efor con star
L channel deglitch signal
pe | we [oe | (et Neee epen)
eae | R channel deglitch signal
(Not used, open)
Interpolation flag
(interpolation at “H’’)
Error flag terminal
Clock (16.9344 MHz) output
(Not used, open)
Test mode selection
(Not used, connected to power
supply.)
Digital signal output
(Not used, open)
Mode selector
(“L”: normal, “H”: SLEEP mode)
(Not used, connected to GND)
Test terminal (“L”: normal)
(Not used, connected to GND)
x Clock output (16.9344 MHz)
2 (Not used, open)
vss GND terminal
Sub-code block (Q data)
clock (75 Hz)
Sub-code frame (Q data)
clock (7.35 kHz)
Sub-code (Q data) output
az Reset signal input (reset at ‘‘L’’)
a Command load signal input
Es MCLK Po Command ciock signal input
| 26 | MDATA a Command data input
Hee Muting control
Tracking servo ON signal
(tracking servo ON at “L”’)
STAT Processing condition
(CRC, CUE, CLVS, TT STOP, FCLV)
SUBC Sub-code serial output data
(Not used, open)
31 SBCK Clock for sub-code serial output
(Not used, open)
[ae [awe [6 [cet na en
VDD Power supply
Emphasis signal input
(Not used, open)
Spindle motor FG signal input
(Not used, open)
Spindle motor ON signal
(ON at “L”)
Spindle motor drive signal
Resynchronizing signal
(Not used, open)
Drop-out signal (Drop-out at ‘‘H")
EFM signal input (DSL)
EFM signal input (PLL)
PLL extract clock input
n
i?)
w N
ow
(eo)
RESY
m
m| 3 m = n
vu
x Cc
2 | (4.3218 MHz)
FPC PLL frequency comparision signal
07
5 vo 16K RAM data input/output
DO
RAM/OE
16K RAM OE signal
16K RAM WE signa!
16K RAM address signal
(RAMAO: LSB, RAMA10: MSB)
RAM/WE
RAM/AO
i)
RAM/A10
eee] are