Technics SL-PS670D

e 1C701 (AN8805SBE1)
Roa > |
Name
1 PD | APC amolifier input
P=
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annie
owed
cron
3
|
LD
ON/OFF
|
I
|
APC
ON/OFF
contro!
signal
REFSW Capacitor connection for CROSS
Vv
Ri
as
Power supply
RF amplifier inversion signal input
RF amplifier signal output
AGC signal input
CAGC AGC loop filter connection
a
=
it
oe
es
eee
0 | AGC signal output
a
fr
CENV
Cc
Capacitor connection for RF detection
Capacitor connection for HPF amplifier
Capacitor connection for-RF envelope
13“ - CSBBO detection
Zz O
Ge
RF-
RF
FIN
ARF
EA
EDO
BDO signal output
15 CSBRT per connection for RF envelope
FTR
/RFDET
Vss
ENV
OFTR signal output
RFDET signal output
3TENV signal output
VREF signal output
APC OFF signal contro!
pare
LD OFF
VDET
TEBPF
CROSS
TEOUT oO
VDET signal output
VDET signal input
CROSS signal output
TE amplifier signal output
TE amplifier inversion signal input
FE amplifier signal output
FE amplifier inversion signal input
FBAL conirol signal
TBAL control signal
Adjustment for I-V amplifier conversion
resister
Adjustment for I-V amplifier conversion
resister
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SL-PS670A
@ IC702(MN662713RG1)
Terminal
Fa
1 1 BCLK © |Bit clock output for serial data
LRCK i LR identification signal output
SRDATA Serial data output
DVddi Power supply input (for digital circuit)
GND (for digital circuit)
™ Digital audio interface signal output
Cl
u
M Microprocessor command clock signal
input (Latches data at first transition)
ee MDATA Microprocessor command data signal
input
M Microprocessor command load signal
input
Sense signal output
SENSE
LIK
D
POSAD, SFG)
Focus servo feeding signal output
(OFT, FESL, MAGEND, NAJEND,
FLOCK (’L”: Feed)
1
Sub-code block clock signal output
(IBLKCK= 75 Hz during normal
playback) (no used, open)
External clock signal input for sub-code
Q resister
Sub-code Q code output
Muting input (“H”: Mute)
Status signal output
(CRC, CUE, CLVS, TTSTVP, FCLV,
SQCK)
Reset input
1
1
1
ca
cee
=:
a
Tracking servo feedi ignal output
[| ros [o oer eee
ie
e
2
BLKCK
sack
STAT
/RST
SMCK
B PMC
Traverse forced feed output
2
2
2
2
° Bl
ka
3 Spindle motor ON signal output
(“Ls ON)
Bi
9
8
1
7
1/2-divided clock signal of crystal
oscillating at MSEL =“H”
(fSMCK = 8.4672 MHz)
1/4-divided clock signal of crystal
oscillating at MSEL ="L”
(ISMCK = 4.2336 MHz)(no used,open)
19
1/192-divided clock signal of crystal
oscillating ((PMCK= 88.2 kHz)
(no used,open)
Spindle motor drive signal output
(servo error signal output)
Kick pulse output
Tracking drive output
Focus drive output
D/A (drive) output (TVD, ECS, TRD,
FOD, FBAL, TBAL) reference voltage
26 KICK
i
2
Spindle motor drive signal output
(forced mode output)
TRV
TVD
PC
ECM
RD
FOD
EF
BAL
BAL
input
Focus balance adjustment output
Tracking balance adjustment output
eS
ees
—31-
SL-PS670A |
e 1C702 Continued
Terminal
fro.| "ame |!
| 32 FE | |Focus error signal input (analog input)
TE Tracking error signal input
(analog input)
RFENV | RF envelope signal input
35 VDET a Vibration detection signal input
Orr st) Off-track signal input (“H”: off track)
ee Track cross signal input
eee Bi ("L’: detection)
| BDO | | | Dropout signal input (“H”: Dropout)
Function
a] w
("H": detection)
RF detection signal input
Laser onsignal output ("H”: ON)
; Play signal out ("H":; PLAY)
(no used, open)
wy Fo | ("H’: Double speed) (no used, open)
[ARF [7 rrsenatinet |
[REF | |fterence curentinpat |
PAF [= [psc bias no used open |
7 DSLF DSL loop filter
PLLF I/O |PLL loop filter
VCOF VCO loop filter
=| Power supply input (for analog circuit)
| AVss2 | — | GND (for analog circuit)
| owe | Double speed status signal output
als] 6] a
OFT
CRS
BDO
4 TES
mb =BEAY-
EL
ARF
DRF
EFM
PLL extraction clock output
PCK (fPCK= 4.321 MHz during normal
playback) (no used, open)
Phase comparison signal of EFM and
PCK signals (no used, open)
SUBC Sub-code serial data output
(no used, open)
| 56 | SBCK i] Clock input for sub-code serial data
2
x4 rystal oscillating circuit input
(f= 16.93844MHz)
x2 Crystal oscillating circuit output
(f= 16.9344MHz)
Power supply input (for osciilating
je] vet |= [ern
| 61 | BYTCK =] Byte clock output (no used, open)
ub-code frameclock signal output
62 /CLDCK ((CLDCK = 7.35kHz during normal
playback)
Crystal frame clock signal output
FCLK = (FCLK = 7.35kKHz, double = 14.7kHz)
Interpolation flag output
ot ee 0 | (‘H": Interpolation) (no used, open)
|} FLAG [0 | Flag output (no used, open)
Tracking error shunt signal output
("H”: shunt) (no used, open)
Function
Terminal
fno.| "name |!
Spindle servo phase synchronizing
signai output
("H": CLV, “L’: rough servo)
(no used, open)
Sub-code CRC checked output
("H”: OK, “L”: NG) (no used, open)
De-emphasis ON signal output
("H”: ON) (no used, open)
Frame resynchronizing signal output
(no used, open)
Reset input through MASH circuit
(“L”: Reset)
ee
ia
a
feet
| OuTR =| 0 | Right channel audio signal output
i
FF signal polarity assignmentinput
(at “H” level: RSEL = “H”)
(at “L” level: RSEL ="L”)
Crystal oscillating frequency
designation input
("L’: 16.9344MHz, “H”: 33.8688MHz)
Test input (normally, “L”)
Output frequency switching for SMCK
terminal
"H”: SMCK = 8,.4672MHz
"L’ SMCK = 4.2336MHz
Output mode switching of SUBQ
terminal (H”: Q code buffer mode)
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