Theory of Operation-2225 Service
lnput Coupling (AC-GND-DC)
A signal from the CH 1
OR
X input connector may be
ac or dc coupled to the High-Impedance Attenuator
circuit or disconnected completely by the lnput
Coupling Switch. Signals from the CH 1
OR
X input
connector are routed through resistor
R1 to lnput
Coupling switch
S101. When S101 is set for dc
coupling, the Channel 1 signal goes directly to the
input of the High-Impedance Attenuator stage.
When ac coupled, the input signal passes through
dc-blocking capacitor C2. The blocking capacitor
stops the dc component of the input signal from
reaching the Attenuator circuit. When switched into
the signal path, attenuator AT1 attenuates the input
signal by factors of 100, 10, 4, or 2. When
51 01 is
set to GND, the direct signal path is opened, and the
input of the attenuator is connected to ground. This
provides a ground reference without the need to
remove the applied signal from the input connector.
The coupling capacitor precharges through R4 to
prevent large trace shifts when switching from GND
to AC.
lnput Attenuator
The effective overall deflection factor of each
vertical channel is determined by the setting of the
Channel VOLTSIDIV switch. The basic deflection
factor of the Vertical system is
5
mV1DIV. For
VOLTIDIV switch settings above
5
mVIDIV,
frequency compensated voltage dividers
(attenuators) are switched into the circuit. Each
channel has
2X, 4X,
1
OX, and 100X attenuators that
are selected in various combinations to produce the
indicated deflection factor. Each attenuator contains
an adjustable series capacitor to provide correct
attenuation at high frequencies and an adjustable
shunt capacitor to provide correct input
capacitance.
Source Follower
The Channel 1 signal from the input attenuator is
connected to source follower
Q13A via,R6 and C6.
Resistor
R5 provides the input resistance. FET Q13B
is a constant current source for Q13A. Transistors
Q13A and Q13B provide a high input impedance for
the attenuator stage and the output drive current
needed for Paraphase Amplifier U30 (the first stage
of amplification).
In the event that excessive high-amplitude signals
are applied to source follower
Q13A, the signal will
be limited by CR7 and the gate-source junction of
Q13A. If an excessive negative-going signal causes
CR7 to become forward biased,
Q13A gate is
clamped to approximately -9.3 V. An excessive
positive-going signal will forward bias the gate-
source junction of
Q13A. As soon as gate current
flows, the gate voltage will stop increasing. Gate
current is limited by the high resistance of R6.
Paraphase Amplifier
Paraphase Amplifier U30 converts the single-ended
signal from Q13 into a differential signal for the
Vertical Preamplifier. The signal from
Q13B pin 2
goes to the base of one transistor in
U30. The other
input transistor in U30 is biased by the divider net-
work formed by
R30, R31, R32, and R33. Emitter
current for the two input transistors is supplied by
R22 and R23. Resistor R29 sets the gain for the
stage. The network formed by
C8 and R9 reduce the
substrate capacitance of Q13 at high frequencies.
R8 biases the diode substrate of Q13 off. The
collector current of the two input transistors serves
as emitter current for the differential output transis-
tor pairs. Base bias voltages for the output pairs are
developed by the divider network formed by
R39,
R41, R42, and Variable VOLTSIDIV potentiometer
R43. The transistors of U30 have matched charac-
teristics, so the ratio of currents in the two transis-
tors,
U83C and U83D, connected as diodes,
determines the current ratios in the output transistor
pairs of U30.
As Variable VOLTSIDIV potentiometer R43 is rotated
from calibrated to uncalibrated, the conduction level
of the transistors connected to R35 increases. Since
the transistor pairs are cross connected, the
increased conduction in one pair of transistors sub-
tracts from the output current produced by the tran-
sistor pair connected to
R38, and the overall gain of
the amplifier decreases. Balance potentiometer R33
is adjusted to balance the amplifier for minimal dc
trace shift as the CH 1 Variable VOLTSIDIV control is
rotated.
Incorporated in the Channel
2
Paraphase Amplifier is
circuitry that allows the user to invert the polarity of
the Channel 2 signal. When CH 2 INVERT switch
S90
is selected for NORM, the transistor pairs in U80 are
biased as they are in U30, and the CH 2 trace is not
inverted. For the CH 2 INVERT position of
S90,
connections to the bases of the output transistor
pairs are reversed, reversing the polarity of the
output signal to produce an inverted Channel 2
trace. Invert Balance potentiometer R83 is adjusted
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