Texas Instruments 99/4A - Page 43

MEMORY SELECTION LOGIC
GENERAL DESCRIPTION
The memory selection logic decodes the more significant address
lines tor selecting fast ROM and RAM memory. Also the output of
the decoder is used for a second decoder, which selects internal
devices such as VDP, sound etc...
HARDWARE DESCRIPTION
The schematics of the memory selection logic with a memory map
is given in Figure 11, p.35. When MEMEN is active, U504
(74LS138) decodes the three most significant address lines AO
through A3, dividing the address space in the following 8 blocks
of 8 bytes.
BLOCK 0
Memory Block 0 (>0000 — >1FFF) is used to select the system read
only memory (ROM).
BLOCK 1
Memory Block 1 (>2000 — >3FFF ) is reserved for memory expansion.
BLOCK 2
Memory Block 2 (>4000 — >4FFF) is used to select read only memory
in external devices, such as RS232 interface. The ROM in these
devices contains the device service routine (MBE).
BLOCK 3
Memory Block 3 (>6000 — >7FFF ) is used for the optional read only
memory in solid state software command modules (RDMG).
BLOCK 4
Memory Block 4 (>8000 — >9FFF ) is used divided in several parts.
Memory locations >8000 to >83FF are used for the fast system
read-and-write memory. This further decoding of the address
space is done in OR-gates U507. This part of ths circuitry also
generates the RAMBLK signed, which is used to select the TMS
9901 programmable system interface. Furthermore the MB4 signal
is used to select a second 74LS138 which divides memory block 4
in more parts.
BLOCK 5, 6 AND 7
These blocks are used along with Block 1 for memory expansion.
START SIGNAL
By combining the CSRAM and ROMEN signals , together with MEMEN
in NAND-gate U606 and OR-gate U605, the START signal is
developed. This signal is used in the 16 to 8 bit interfacing
c i r c u i t .