Texas Instruments AM1808 - Page 150

2
1
CLKS
FSRexternal
CLKR/X(noneedtoresync)
CLKR/X(needsresync)
Bit(n1) (n2) (n3)
Bit0 Bit(n1) (n2) (n3)
14
12
11
10
9
33
2
8
7
6
5
44
3
1
3
2
CLKS
CLKR
FSR(int)
FSR(ext)
DR
CLKX
FSX(int)
FSX(ext)
FSX(XDATDLY=00b)
DX
13 (A)
13 (A)
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
A. No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 6-32. McBSP Timing
Table 6-65. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-33)
1.3V, 1.2V 1.1V 1.0V
NO. UNIT
MIN MAX MIN MAX MIN MAX
1 t
su(FRH-CKSH)
Setup time, FSR high before CLKS high 4 4.5 5 ns
2 t
h(CKSH-FRH)
Hold time, FSR high after CLKS high 4 4 4 ns
Table 6-66. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-33)
1.3V, 1.2V 1.1V 1.0V
NO. UNIT
MIN MAX MIN MAX MIN MAX
1 t
su(FRH-CKSH)
Setup time, FSR high before CLKS high 5 5 10 ns
2 t
h(CKSH-FRH)
Hold time, FSR high after CLKS high 4 4 4 ns
Figure 6-33. FSR Timing When GSYNC = 1
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