Texas Instruments AM1808 - Page 156

AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Table 6-70. Additional SPI0 Master Timings, 4-Pin Enable Option
(1)(2)(3)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
3P+5 3P+5 3P+6
to SPI0_CLK rising
Polarity = 0, Phase = 1,
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
to SPI0_CLK rising
Delay from slave assertion of SPI0_ENA
17 t
d(ENA_SPC)M
ns
active to first SPI0_CLK from master.
(4)
Polarity = 1, Phase = 0,
3P+5 3P+5 3P+6
to SPI0_CLK falling
Polarity = 1, Phase = 1,
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
to SPI0_CLK falling
Polarity = 0, Phase = 0,
0.5M+P+5 0.5M+P+5 0.5M+P+6
from SPI0_CLK falling
Polarity = 0, Phase = 1,
P+5 P+5 P+6
Max delay for slave to deassert SPI0_ENA
from SPI0_CLK falling
18 t
d(SPC_ENA)M
after final SPI0_CLK edge to ensure ns
Polarity = 1, Phase = 0,
master does not begin the next transfer.
(5)
0.5M+P+5 0.5M+P+5 0.5M+P+6
from SPI0_CLK rising
Polarity = 1, Phase = 1,
P+5 P+5 P+6
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-68).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option
(1)(2)(3)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
2P-1 2P-2 2P-3
to SPI0_CLK rising
Polarity = 0, Phase = 1,
0.5M+2P-1 0.5M+2P-2 0.5M+2P-3
to SPI0_CLK rising
Delay from SPI0_SCS active to first
19 t
d(SCS_SPC)M
ns
SPI0_CLK
(4) (5)
Polarity = 1, Phase = 0,
2P-1 2P-2 2P-3
to SPI0_CLK falling
Polarity = 1, Phase = 1,
0.5M+2P-1 0.5M+2P-2 0.5M+2P-3
to SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-68).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
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