Texas Instruments AM1808 - Page 216

UHPI_HAS
(D)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE
(A)(C)
UHPI_HCS
UHPI_HD[15:0]
(input)
UHPI_HRDY
(B)
2
1
2
1
1
2
2
1
2
1
1
2
3
4
3
11
12
18
13
5
185
11
12
13
2nd Half-Word1st Half-Word
A. UHPI_HSTROBE
refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR
UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on UHPI_HRDY
may or may not occur.
C. UHPI_HCS
reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS
timing requirements are reflected by parameters for UHPI_HSTROBE.
D The diagram above assumes UHPI_HAS has been pulled high.
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Figure 6-67. UHPI Write Timing (HAS Not Used, Tied High)
216 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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