Texas Instruments TMS320C6000 Series - Interrupt Set Register (ISR); Interrupt Clear Register (ICR)

Individual Interrupt Control
7-15 Interrupts
Note:
Any write to the ISR or ICR (by the MVC instruction) effectively has one delay
slot because the results cannot be read (by the MVC instruction) in the IFR
until two cycles after the write to the ISR or ICR.
Any write to the ICR is ignored by a simultaneous write to the same bit in the
ISR.
Example 7–6 and Example 7–7 show code examples to set and clear individu-
al interrupts.
Figure 7–8. Interrupt Set Register (ISR)
31
16
Reserved
15
0
IS15
IS14 IS13 IS12 IS11 IS10
IS9 IS8 IS7 IS6 IS5 IS4
W
Rsv Rsv Rsv Rsv
Legend: W = Writeable by the MVC instruction
Rsv = Reserved
Figure 7–9. Interrupt Clear Register (ICR)
31
16
Reserved
15 0
IC15
IC14 IC13 IC12 IC11 IC10
IC9 IC8 IC7 IC6 IC5 IC4
Rsv
Rsv
Rsv
Rsv
W
Legend: W = Writeable by the MVC instruction
Rsv = Reserved
Example 7–6. Code to Set an Individual Interrupt (INT6) and Read the Flag Register
MVK 40h,B3
MVC B3,ISR
NOP
MVC IFR,B4
Example 7–7. Code to Clear an Individual Interrupt (INT6) and Read the Flag Register
MVK 40h,B3
MVC B3,ICR
NOP
MVC IFR,B4