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Texas Instruments TMS320C67X - Page 370

Texas Instruments TMS320C67X
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Functional Unit Constraints
Pipeline4-38 SPRU733
Table 422 shows the instruction constraints for ADDDP/SUBDP instructions
executing on the .S unit.
Table 422. ADDDP/SUBDP .S-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5 6 7
ADDDP/SUBDP R R W W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle Xr Xw Xw
2-cycle DP Xr Xw Xw Xw
DP compare
Xr Xw Xw
ADDDP/SUBDP
Xr 
ADDSP/SUBSP
Xr Xw Xw 
Branch
Xr 
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr
DP compare Xr 
2-cycle DP
Xr 
4-cycle
Xr 
Load

Store

Branch
Xr 
16 × 16 multiply
Xr 
MPYI
Xr 
MPYID
Xr 
MPYDP
Xr
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle-read/
decode constraint; Xw = Next instruction cannot enter E1 during cyclewrite constraint