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Texas Instruments TMS320C67X - Page 369

Texas Instruments TMS320C67X
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Functional Unit Constraints
4-37PipelineSPRU733
Table 421 shows the instruction constraints for ADDSP/SUBSP instructions
executing on the .S unit.
Table 421. ADDSP/SUBSP .S-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4
ADDSP/SUBSP R W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle Xw
2-cycle DP Xw Xw
DP compare
Xw
ADDDP/SUBDP

ADDSP/SUBSP

Branch
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xw = Next instruction cannot enter E1 during cyclewrite
constraint