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Texas Instruments TMS320C67X User Manual

Texas Instruments TMS320C67X
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Control Register File
2-15CPU Data Paths and ControlSPRU733
Table 27. Control Status Register (CSR) Field Descriptions (Continued)
Bit DescriptionValueField
75 PCC 07h Program cache control mode. Writable by the MVC instruction. See the
TMS320C621x/C671x DSP Two-Level Internal Memory Reference Guide
(SPRU609).
0 Direct-mapped cache enabled
1h Reserved
2h Direct-mapped cache enabled
3h7h Reserved
42
DCC 07h Data cache control mode. Writable by the MVC instruction. See the
TMS320C621x/C671x DSP Two-Level Internal Memory Reference Guide
(SPRU609).
0 2-way cache enabled
1h Reserved
2h 2-way cache enabled
3h7h Reserved
1
PGIE Previous GIE (global interrupt enable). Copy of GIE bit at point when
interrupt is taken. Physically the same bit as SGIE bit in the interrupt task
state register (ITSR). Writeable by the MVC instruction.
0 Disables saving GIE bit when an interrupt is taken.
1 Enables saving GIE bit when an interrupt is taken.
0
GIE Global interrupt enable. Physically the same bit as GIE bit in the task state
register (TSR). Writable by the MVC instruction.
0 Disables all interrupts, except the reset interrupt and NMI (nonmaskable
interrupt).
1 Enables all interrupts.

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Texas Instruments TMS320C67X Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320C67X
CategoryComputer Hardware
LanguageEnglish

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