NINA-W1 series - User Manual
The u-connectXpress software adds the DSR and DTR pins to the UART interface. Not used as they
were originally intended, these pins are used to control the state of NINA modules.
Depending on the configuration, DSR can be used to:
Enter command mode
Disconnect and/or toggle connectable status
Enable/disable the rest of the UART interface
Enter/wake up from sleep mode
The functionality of the DSR and DTR pins are configured by AT commands. For further information
about these commands, see the u-blox Short Range Modules AT commands manual.
Table 1 shows the default settings of UART ports when using u-connectXpress software.
Interface Default configuration
UART interface 115200 baud, 8 data bits, no parity, 1 stop bit, hardware flow control
Table 1: UART port default settings
It is advisable to make UART0 available either for test points or connect it to a header for firmware
upgrade. The IO level of the UART follows VCC_IO.
For information about UART interface characteristics, see the NINA-W1 series Data Sheets.
1.6.2 Ethernet (RMII+SMI)
⚠ On NINA-W13, RMII is supported from software version 2.0.0 onwards.
⚠ On NINA-W15, direct MAC to MAC connection will be supported when the module reaches
Engineering Sample status.
NINA-W1 series modules include a full RMII for Ethernet MAC to PHY communication using the
included Station Management Interface (SMI). The RMII and SMI uses nine signals in total. The
interface requires an external 50 MHz clock source either from a compatible PHY chip or from an
external oscillator.
The two-wire SMI is used to configure the PHY chip. It uses a clock line and a data line to setup the
internal registers on PHY chip.
The pin multiplexing of the RMII interface imposes limitations in the functionality of NINA-W13/W15
series module when using the interface. The following functions are turned off when RMII
communication is initiated:
Red, Green and Blue LEDs are disabled
UART is run without flow control as CTS and RTS functionality is disabled
DSR and DTR functionality is disabled
A 1.5 kΩ pull up resistor must be added to MDIO pin.
1.6.2.1 Startup precautions
To ensure that the boot mode is not entered inadvertently, the RMII_CLK input (GPIO27) is
multiplexed with the ESP boot pin and must be held high 1.2 ms after the reset signal is released.
EVK-NINA-W1 uses two buffers and a low pass filter to delay the reset signal going to the PHY
circuit, as shown in Figure .
This delays the clock so that it starts a short time after the module is released from reset.
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