CHAPTER5. MAJOR IC INFORMATIONS
[1]MAJOR IC INFORMATIONS
1.1. U502 (
V6 7602B0 CFE3
)
The Sigma Designs’ V6 7602, is an integrated 60/120Hz Multi-Format Decoder smart TV SoC with
all the key technologies required for advanced connectivity. This single-chip solution supports
channel decoding, audio decoding and encoding, video decoding, audio and video
post-processing, 3D formatting, quad LVDS output, and smart TV functionality, enabled by a
high-performance CPU and GPU. Features include ATSC/DVB-T/DVB-C/ISDB-T and analog
demodulators, a secure programmable transport stream demultiplexer, high-performance 3D
graphics, 3DTV-capable video decoder, programmable audio decoder, and video post-processor
based on Sigma Designs’ industry-leading video processing algorithms. V6 7602 is ready for the
next generation of smart TVs by supporting advanced 2D to 3D conversion, FHD video processing,
and full-screen 16:9 support with uncompromising picture quality. A 1.2GHz ARM A9 dual-core
host CPU enables advanced connectivity and OTT services for the next generation smart TV. A
quad-core ARM Mali GPU provides fast 2D/3D graphics acceleration. To enable fast time to
market, V6 7602 comes with production-proven software solutions for all major geographical
regions
Key Features
• Dual-core A9 with 512KB L2 cache
• Quad-core ARM MALI 3D GPU
• Secure CPU with ARM trust zone
• Simultaneous 2x HDMI RX for PIP/POP
• DVB-C/ATSC/DVB-T/ISDB-T channel demodulator
• Analog VIF and SIF demodulator
• Multi-format audio/dual FHD video decoder
• Advanced audio/FHD video processing
• 3D formatter
• Peripheral and power management
1.2. U505, U506 , U507(
2Gb DDR3 SDRAM F-Die
)
Description
The 2Gb Double-Data-Rate-3 (DDR3(L)) B-die DRAM is double data rate architecture to achieve
high-speed operation. It is internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices.
These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866
Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3(L) DRAM
key features and all of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
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