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Virtex-5 FPGA ML550
Xilinx Virtex-5 FPGA ML550 - User Manual
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R
Vir
te
x-5 FPGA ML550
Netw
orking Interfaces
Platf
orm
User Guide
UG202 (v1.4) Ap
ril 18, 2008
Downloaded from
Elcodis.com
electronic components distributor
2
Table of Contents
Main Page
default chapter
3
Table of Contents
3
Additional Documentation
7
Guide Contents
7
Preface: about this Guide
7
Additional Support Resources
8
Online Document
9
Typographical Conventions
9
Chapter 1: Introduction
11
About the Virtex-5 FPGA Source-Synchronous Interfaces Tool Kit
11
Virtex-5 FPGA ML550 Networking Interfaces Development Board
12
Chapter 2: Getting Started
15
Documentation and Reference Design CD-ROM
15
Quick Start Guide
15
Initial Setup
15
Check Kit Contents
15
Unpack the Kit and Make Connections
15
Installation
16
Silicon Labs USB-To-RS232 Bridge Chip Driver Installation
16
BERT GUI Tcl Interface Installation
17
ML550 Board Startup and Operation
17
Programmable Clock Module Switch Position Chart
18
Four-Pole SW DIP2 Settings
18
Eight-Pole SW DIP1 Settings
18
Chapter 3: Hardware Description
19
Clock Generation
20
SDRAM Memory
21
Liquid Crystal Display
22
Display Hardware Design
23
Hardware Schematic Diagrams
24
User LED
25
Configuration INIT and DONE Leds
26
User Push-Button Switches
26
Program Switch
27
USB Port (J22)
27
LVDS Connectors
28
Transmit LVDS
28
Receive LVDS
28
LVDS Loopback Board (Xilinx P/N 0431395)
29
Voltage Regulators (TI PTH05000)
29
Voltage Regulator ±5% Margin Adjustment (in 2.5% Increments)
29
Important Note about ± 5% Margin Limits
31
Power Monitor Connector
32
ML550 System Monitor and Power Monitor Support
34
ML550 Board System Monitor Support Circuitry Details
36
5V Input Power Voltage Monitor
36
CCAUX Voltage Monitor
37
CCO Voltage Monitor
37
2.5V System Power Voltage Monitor
38
CCINT Voltage Monitor
38
5V Input Power Current Monitor
39
PCB Temperature Monitor
39
REF System Monitor
40
J19 Mezzanine Board Connector
41
Power Monitor Circuitry
43
Power Monitor Board
44
Data Sheet References
44
Chapter 4: Configuration
45
Configuration Modes
45
JTAG Chain
46
JTAG Ports
47
MM Flat Cable Port
48
System ACE Interface
49
Appendix A: LVDS
51
LVDS Transmit Connectors
51
LVDS Receive Connectors
56
Appendix B: LVDS Loopback Board
61
Appendix C: LCD Interface
63
General
63
Display Hardware Design
63
Hardware Schematic Diagram
64
Peripheral Device KS0713
65
Controller - Operation
67
Controller - LCD Panel Connections
70
Controller - Power Supply Circuits
72
Operation Example of the 64128EFCBC-3LP
73
Instruction Set
76
Read/Write Characteristics (6800 Mode)
79
Design Examples
80
LCD Panel Used in Full Graphics Mode
80
LCD Panel Used in Character Mode
81
Array Connector Numbering
85
UCF Information
85
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Xilinx Virtex-5 FPGA ML550 Specifications
General
Brand
Xilinx
Model
Virtex-5 FPGA ML550
Category
Network Hardware
Language
English
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