Zenith J584W - Page 23

FIGURE 6 - CHASSIS 3WJR52 FM RF SCHEMA TIC
FM - RF
k Q1, the RF amplifier, is a Dual Insulated Gate MOS Field
* Effect Transistor (See Figure 6). FM Antenna coil (L1), FM
RF coil (L2), and Oscillator coil (L4) are all precisely tuned
to insure that the tuner will reject unwanted and undesired
combinations of RF signals present in many areas due to
todays complex communication systems. Coil L3 is part of
a 10.7 Megahertz trap in the emitter lead of the Mixer tran 
sistor (Q2).
Under no signal conditions, voltages are applied as follows to
the MOSFET elements of Q1. Resistors R1 and R4 form a
voltage divider across the B+ line providing a fixed bias to
Gate 1 (G1). The FM RF signal from L1 is also applied to
G1. Delayed AGC voltage from pin 15 of the FM IF IC201 is
applied, via R202 and R2, to G2 of Q1. Under no signal
conditions the G2 voltage will be approximately 4.6 volts.
Q1 drain voltage is applied from B+ via R6, the RF coil
L2 and R5.
At this point lets recap the existing voltage conditions:
Gate 1 to Source — approx. — 0.0 volts,
Gate 2 to Source — approx. +2.6 volts,
Drain to Source — approx. +9.0 volts,
Drain current — approx. 10 milliamp.
(A variation can be expected due to circuit component
tolerances.)
. As the gain of the IF stages in IC201 increases, reverse AGC
| voltage will be developed at IC201 (pin 15) and applied to
terminal /02) of the RP Amplifier Q1. This increasing
AGC voltage, when added to the gate bias voltage, will cause
the gate voltages to go more negative, driving the FET toward
cut-off. When this occurs, the current flow is reduced, there 
by reducing the FET's gain. This stage is designed for optimum
circuit performance and minimum noise. In this application,
the drain current is at approximately one-half of the saturation
current.
MOSFET PROTECTION
When these devices are being handled out of circuit, it is
possible for static charges to build up between gate and source.
This charge could reach a value which would exceed the gate
breakdown voltage. To reduce this condition, MOSFET'S
of early design would be shipped with all leads twisted to 
gether, or with a wire wrapped around all leads. Since all
leads were shorted together, there would be no impedance
across which a voltage could develop.
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FIGURE 7 - MOSFET GA TE PROTECTION