3. Extended Immediate Addressing
4. Register Addressing
5. Register Indirect Addressing
6. Extended Addressing
7. Modified Page Zero Addressing
8. Relative Addressing
9. Indexed Addressing
10. Bit Addressing
IMPLIED ADDRESSING
In this kind of addressing, the operation code of the instruction
is fixed. There are no variable
fields
within the instruction, and the
instruction always performs exactly the same function. Examples of
this kind are the CPL and LD SP, IY instructions.
The format of the CPL, Complement Accumulator, is shown in
Fig. 4-1. This instruction takes the contents of the A register, forms
the ones complement (changes all zeros to ones and all ones to
zeros) and stores the result back into the A register. No condition
code bits are affected. The
source
and
location
are fixed and no
other register can be used.
CPL COMPLEMENT ACCUMULATOR
BYTE 0
7
2FH -OP CODE
0
10 0 1 0 1 1 1 1
Fig. 4-
1. Implied addressing in
CPL instruction.
The format of the LD, SP, IY instruction is shown in Fig. 4-2.
Load SP with IY takes the 16-bit contents of the IY register and
transfers it to the SP register. The contents of the IY register re-
mains unchanged and no condition-code bits are affected. The two-
byte configuration FDF9H will always produce the same action of
loading the SP register from the IY register.
LD SP,IY LOAD SP WITH IY
7 0
Fig. 4-2
.
Implied addressing in LD
BYTE 0
1 1 1 1 1 1 0 1
FDH 1
SP,IY instruction.
BYTE
1
1 1 1 1 1 0 0 1
OP CODE
F9H J
All of the instructions discussed in the next chapter under General-
Purpose Arithmetic and CPU Control are of this kind, as are the
instructions under the Exchange, Block Transfer, and Search Group.
In the latter group, the actions are more elaborate, but the instruc-
tion format is fixed.
42
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