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stack allows simple implementation of multiple level interrupts, unlimited
subroutine nesting and simplification of many types of data manipulation.
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The two independent index registers hold a 16-bit base address that is
used in indexed addressing modes. In this mode, an index register is used
as a base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify
a displacement from this base. This displacement is specified as a two’s
complement signed integer. This mode of addressing greatly simplifies
many types of programs, especially where tables of data are used.
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The Z80 CPU can be operated in a mode where an indirect call to any
memory location can be achieved in response to an interrupt. The
I
register is used for this purpose and stores the high order eight bits of the
indirect address while the interrupting device provides the lower eight bits
of the address. This feature allows interrupt routines to be dynamically
located anywhere in memory with minimal access time to the routine.
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The Z80 CPU contains a memory refresh counter, enabling dynamic
memories to be used with the same ease as static memories. Seven bits of
this 8-bit register are automatically incremented after each instruction
fetch. The eighth bit remains as programmed, resulting from an LD R, A
instruction. The data in the refresh counter is sent out on the lower portion
of the address bus along with a refresh control signal while the CPU is
decoding and executing the fetched instruction. This mode of refresh is
transparent to the programmer and does not slow the CPU operation. The
programmer can load the
R register for testing purposes, but this register
is normally not used by the programmer. During refresh, the contents of
the
I register are placed on the upper eight bits of the address bus.