Acer G185H - Page 32

SPEC NO.
M T1 8 5GW 0 1 V. 0
PAGE
9/23
Note 4 : test condition :‘
(1) V
DD
= 5 V, V
DD
rising time = 470 µs ± 10%
(2) Pattern: Mosaic pattern
(3) Test circuit
Note 5: LVDS signal definition
VID = VIN
+
– VIN- ,
ΔVCM =｜VCM
+
–VCM-｜,
ΔVID =｜VID
+
–VID-｜,
VID+ =｜VIH
+
–VIH-｜,
VID- =｜VIL
+
–VIL-｜,
VCM = (VIN
+
+VIN-)/2,
VCM+ = (VIH
+
+VIH-)/2,
VCM- = (VIL
+
+VIL-)/2,
90
%
Ton=470
μ
s ± 10%
V
DD
5 V
12V
VDD ( LCD INPUT)
CONTROL SIGNAL
(HIGH to LOW)
M2
2SK1399
M1
2SK1059
R2
1K
C2
10000pF
C3
1uF
R3
47K
R1
47K
FUSE
C1
1uF
VIN
+
= Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input