SCLK (Sys Clock) - Optional 27 MHz 'video mode'
ssytem clock input - by default we generate the
sysclock from the WS clock in 'audio mode' But
the UDA can also take a oscillator input on this pin
Mute - Setting this pin High will mute the output
De-Emphasis - In audio mode (which is the
default), can be used to add a de-emphasis filter.
In video mode, where the system clock is
generated from an oscillator, this is the clock
output.
PLL - sets the PLL mode, by default pulled low for
Audio. Can be pulled high or set to ~1.6V to set
PAL or NTSC video frequency
SF0 and SF1 are used to set the input data format. By
default both are pulled Low for I2S but you can change
them around for alternate formats.
See the back of the PCB for a quick reference
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