Akai AC-410

CXA1782BQ (CD RF I-V AMP/RF AMP)
PIN
No.
|
PORT
NAME
VO
FUNCTION
|
1
FEO
Focus
drive
output.
2
FEI
|_|
Focus
error
signal
input.
3___|
FDFCT
Connect
condenser
for
Focus
servo
gain
control.
5
FLB
|
|
Connect
condenser
for
Focus
servo
correction.
6
FE-O
O
|
Focus
drive
output.
7
FE-M
|
|
FOCUS
AMP
Inverting
input.
8
SRCH
|
|
Connect
condenser
for
Focus
search
wave.
9
|
TGU
[1
|
Connect
condenser
for
Trackink
gain
select,
10
TG2
|
|
Connect
condenser
for
Tracking
gain
select.
11
FSET
|
|
Terminal
for
peak
setting
for
Focus
tracking
phase
compensation.
12
TA-M
|
|
Tracking
AMP
Inverting
input.
fs
Ae
|
WO
ee
OY
Tracking
drive
output.
on
tS
SL-P
|
|
Sled
AMP
non-inverting
input.
15
|
SLM
[1
[Sled
AMP
inverting
input
16
SL-O
O
|
Sled
drive
output.
17
ISET
|
Focus
search,
Track
jump
and
slide
kick
current
input.
[18
vec
~
|
45V
19
CLK
|
|
Clock
signal
input
from
the
CD
MI-COM.
20
XLT
|
|
Lutch
signal
input
from
the
CD
MI-COM.
[21
|
DATA
|_|
Data
signal
input
from
the
CD
MI-COM.
22
XRST
|
|
RESET
input.
[
23
|
C.OUT
O
|
Track
count
signal
output.
|
24
SENS
__|
O
|
FZC,DFCT,TZC,GAIN
and
BAL
output.
25
FOK
©
|
Focus
OK
signal
output.
26
eee
|
Input
terminal
of
DEFECT
bottom
hold
output
which
is
supplied
through
capcitor.
|
27
|
cc
O
|
DEFECT
bottom
hold
output
terminal.
28
CB
__|_
|
|
DEFECT
bottom
hold
capacitor
connecting
terminal.
a6
cp
Terminal
for
connection
of
MIRR
hold
capacitor.
(Non
inverted
input
terminal
of
i
nil
MIRR_
comparator.)
|
_30
RF-I
|
|
Input
terminal
of
RF
summing
AMP
output
which
is
supplied
through
a
capacitor.
31
|
RF-O
O
|
RF
summing
AMP
output.
=
32
ee
RF-M
RF
summing
AMP
inverted
input
terminal.
33
LD
©
|
APC
AMP
output
terminal.
|
34
__|
PHD
APC
AMP
input
terminal.
35
PHD1
RF
I-V
AMP
inverted
input
terminal
(for
photo
diode
A+C
of
pick
up)
[36
PHD2
|
RF
|-V
AMP
inverted
input
terminal
(for
photo
diode
B+D
of
pick
up
37
FE-BIAS
Terminal
for
bias
adjustment
of
focus
error
amp.
[38
iF
|
RF
|-V
AMP
inverted
input
terminal
(for
photo
diode
F
of
pick
up)
39
E
RF
|-V
AMP
inverted
input
terminal
(for
photo
diode
E
of
pick
up)
40
El
|
—
|
Not
used
At
VEE
[—
[GND
=
42
mak
TEO
Le
i
Tracking
error
amp
output
terminal.
(E-F
signal
output.)
43
LPF
|
|
BAL
adjustment
of
comperator
input
terminal.
44
TEI
as
Tracking
error
input
terminal.
L.
45
ATSC
|
|
Window
comperator
input
input
terminal
for
ATSC
detection.
46
TZC
|
F
input
terminal
of
tracking
zero
cross
comparator.
47
TDFCT
~
|||
Time
constant
capacitor
connecting
terminal
at
time
of
defect.
48
VC
O
|
(Vcc+VeEEV2
DC
voltage
output
terminal.
LC7073M (RDS DATA PROCESS)
RDS DEMODULATION
DATA INPUT
RDS DEMODULATION
CLOCK INPUT
16
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A
-¢
4
ERROR DETECT a PARALLEL/SERI AL i
“CORRECTION CONVERTOR SERTAL DATA SOUNEUT
SERITAL/PARALLEL
CONVERTOR
SERIAL CLOCK OUTPUT
SYNCHRONIZING
DETECT
START SIGNAL OF
SERIAL DATA OUTPUT BLOCK
RDS RECEIVE DATA OUTPUT
CLOCK OUTPUT
CLOCK INPUT
RESET INPUT
CLOCK OUTPUT POLARITY
x
re)
we
K
=:
a
rut
b
Oo
WW
wel
WwW
Yn
<
EK
<
a
ad
ft
x
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CXD2508AQ
(CD
DIGITAL
SIGNAL
PROCCESS
&
SYSTEM
CONTRO!
NI O}ay-
12, 53
15
Vss
DATO
SPOC
XLSL
LD ON/OFF
MON
control.
Pin
No.
|
PORT
NAME
VO
Fut
1
SCOR
O
|
H
output
when
either
sub
code
$
2
SBSO
O
|
Serial
output
of
Sub
P
to
W.
3
EXCK
|
|
Clock
input
for
SBSO
read
out.
SQSO
O
|
Serial
output
of
SUBQ
80
bit.
SQCK
|
|
Clock
input
for
SQSO
read
out.
H: MUTE, L: |
SENS output. Output to the OPE
System reset. Reset at L.
Serial data input from THE OPE
Latch input from the OPERATIO
edge of the pulse.)
GND
Serial data transmission clock in
Sense input from SSP.
14
CNIN
Track
jump
number
count
signal
Serial
data
output
to
SSP.
Serial
data
latch
output
to
SSP.
|
Serial
data
transmission
clock
o!
Innermost position ON/OFF dete
Innermost position ON/OFF dete
Innermost position ON/OFF dete
X'tal selection input terminal. L w
Not used
27
LOCK
Not used
Laser diode ON/OFF control.
Focus OK input terminal. For SI
25
MDP
O
|
Servo
control
for
spindle
motor.
26
MDS
—
|
Not
used
Regular GND for TEST terminal
28 TEST -
29 FILO O | Fil
30 FILI
PCO
34
31
33, 75, 76
AVss1 ~3
ae
O
GND
ter output for master PLL. (sle
Filter input for master PLL.
Charge pump output for master
CLTV
42
36 RF
37 BIAS
38 ASYI
VCO control voltage input for m
EFM signal input.
Asymmetry circuir constant cur
Asymmetry compilasion voltage
EFM full swing output.
Not used
L = Vss
circuit OFF H:,
D/A interface for 48 bit slot. LR
LR clock input to DAC.
Serial data from D/A interface.
Audio data input to DAC.
46 Bit clock from D/A interface.
Bit clock input to DAC.
48 | GTOP el
49___| XUGF _[=
50 XPCK =
51 GFS -
52 RFCK -
a an C2PO _|_=_|} Not used
55 __| XROF fe
56 me ad
57 MNT1 -
[58 MNTO z
59 FSTT -
60 C4MR eal
61 DOUT O | Digital out terminal.
62 EMPH O | H output when a playback disc
63 EMPHI | | De-emphasis control input. (H |
=
64
|
WFCK
O
|
WFCK
(Write
Frame
Clock)
ou
65 ZEROL — | Not used
66 ZEROR — | Not used
67, 79, 80 | DTS1~3 - | GND
69
NLPWM
O
|
L-ch
PWM
output.
(opposite
pt
70 LPWM O | L-ch PWM output. (in-phase)
73 XTAI | | 33.8688 MHz X'tal oscillation c
74 XTAO O | 33.8688 MHz X'tal oscillation c
77 NRPWM O | R-ch PWM output. (opposite p
| __78 RPWM O | R-ch PWM output. (in-phase)