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General| Architecture | K10 |
|---|---|
| Process | 45nm |
| Cores | 2, 3, 4, 6 |
| Socket | AM2+, AM3 |
| Integrated Graphics | No |
| Base Clock | 2.5 GHz - 3.7 GHz |
| L2 Cache | 512 KB per core |
| L3 Cache | Up to 6 MB |
| TDP | 65W to 140W |
| Memory Support | DDR2 |
Covers AMD64 technology instruction set extensions, 64-bit integer registers, and 48-bit addresses.
Details triple-core or quad-core options, AMD Balanced Smart Cache, and L1, L2, L3 cache structures.
Describes L1 Data, L1 Instruction, L2, and L3 cache configurations and latencies for Phenom II processors.
Highlights the AMD Wide Floating-Point Accelerator and its 128-bit Floating-Point Unit (FPU).
Details SVM disable/lock, nested paging, Rapid Virtualization Indexing, and world-switch speed.
Covers low-power states, AMD Cool'n'Quiet 3.0, and dynamic power management technologies.
Details ACPI compliance, processor performance states C0-C1E, S0-S5 support.
Specifies DDR2 SDRAM (SSTL_1.8) and DDR3 SDRAM (JEDEC 1.5-V) compliance.
Describes HyperTransport 1 and 3 support, link capabilities, and data rates.
Covers AMD Memory Optimizer Technology, low-latency, prefetching, ECC, and DIMM support.
Details the 144-bit DDR2 SDRAM controller for AM2r2 packages.
Details the 144-bit DDR3 SDRAM controller for AM3 packages.
Lists RoHS compliance and details for AM2r2 and AM3 package types.
Details AM2r2 socket compatibility with AM2, AM2r2, and AM3 package processors.
Details AM3 socket compatibility with AM3 package processors.
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