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APG SPDS12S - Introduction

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DYNAMIC PROCESSORS 3
INTRODUCTION
The SPDS processors are designed to operate in conjunction with DS series speakers and sub-woofers,
optimizing equalization, filtering, protection and distribution of signals.
Each channel comprises and HF EQ stage, a LF EQ stage and a LF protection circuit, as well as a
dynamic protection system which emulates the main operating parameters of the speakers.
Left and Right input signals are mono-combined to feed the subwoofer channel which includes a VLF
EQ stage a level control, a VLF protection circuit, and a dynamic protection circuit.
When used without sub-woofer the unit provides suitable low-Frequency equalization and protection.
A switch allows operation with or without sub-woofer.
An internally derived mono signal is used to feed the sub-woofer output.
The crossover uses a Linkwitz-Riley function with 24 dB/octave slope.
The sub-woofer output level is adjustable with a front panel potentiometer.
The SPDS series feature electronically balanced inputs and outputs, in conjunction with a ground loop
eliminator circuit.
The polarity of the sub-woofer signal can be reversed in order to compensate wiring problems or
acoustical phase reversals.
A quarter-wave delay can be inserted to optimise time alignment.
The sub-woofer equalization can be chosen at 35 or 45Hz
The High frequency stacking equalization provides compensation of relative HF loss due to coupling
effect in multiple configurations.
The system can operate in wide-band mode or in bi-amped mode, with 24 dB/octave slopes. High and
low mute switches are provided.