Apple Apple-1 - System Expansion; Apple-1 System Expansion Capabilities

SECTION
III
HOW
TO
EXPAND
THE APPLE
SYSTEM
The
Apple
system
can
be expanded
to in-
clude more
memory and
IO devices,
via
a
44-pin
edge
connector.
The
system
is fully expandable
to
65K,
with
the
entire
data
and
address
busses,
clocks, control
signals
(
i. e.
IRQ,
NMI, DMA,
RDY, etc.),
and power
sources
available
at
the
connector.
All
address
lines
are TTL
buffered,
and
data
lines
can
drive ten
equivalent
capacitive
loads (one TTL
load and
130pf) without
external
buffers.
All
clock
signals
are TTL.
The
Apple
system
runs
at
approximately 1
MHz
{
see
spec
sheet) and
is fully
compatible
with
6800/6500
style
timing.
Three
power
sources are
available
at the
edge
connector:
+5 volts
regulated,
and
raw DC
(approximately
+/-
14V) for the
+12V, -12V,
and
-5V supplies. If
+12V, -12V,
or
-5V
supplies are
required,
EXTERNAL
REGULATORS
MUST
BE
USED.
An
excess
of
1.5
amps from
the
"on-
board"
regulated
+-5V supply
is
available
for
ex-
pansion
(assuming
suitable
transformer
ratings
are employed).
Exercise
great care in
the
handling
of the raw DC,
as no
short-circuit
protection
is
provided.
REFRESH:
Four
out of
every
65 clock
cycles
is dedi-
cated to
memory
refresh.
At
the start of
a
re-
fresh cycle
(150
ns
after
leading
edge of
01),
RF
goes
low,
and
remains
low
for
one
clock
cycle.
02
is
inhibited
during
a refresh
cycle,
and
the
processor
is held
in
01
(it's inactive state). Dy-
namic
memories,
which
must
clock
during
refresh
cycles,
should
derive their
clock
from
00,
which
is equivalent
to
02,
except that
it
continues
during
a refresh
cycle.
Devices,
such as
PIA's,
will not
be affected
by a
refresh
cycle, since they
react
to
02
only.
Refer
to
Apple "Tech
Notes"
for a
variety
of interfacing
examples.
DMA:
The
Apple
system
has full DMA
capability.
For
DMA,
the DMA
control
line
tri
-
states the
address
buss, thus
allowing
external
devices
to
control the
buss.
Consult
MOS
TECHNOLOGY
6502
Hardware
Manual for
details.
(For
DMA
use,
the
solder
jumper
on the
board,
marked
"DMA",
must
be
broken.
)
For
the 6502
microprocessor,
the
RDY
line
is
used to halt
the
processor
for
single step-
ping, or slow ROM
applications.
Refer
to Apple
"Tech
Notes"
for
examples.
SOFTWARE
CONSIDERATIONS:
The
sequences listed
below are
the
routines
used
to
read
the
keyboard
or output
to
the display.
Read
Key
from
KBD:
jfLDA
KBD
CR (D011)
V
BPL
LDA
KBD DATA
(D010)
Output
to
Display:
*BIT
DSP
(D012)
I
BPL
STA
DSP (D012)
PIA
Internal
Registers:
KBD
Data
D010
High
order
bit
equals
1.
KBD Control
Reg. D011
High
order
bit indicates
"key ready".
Reading
key
clears
flag.
Rising
edge
of KBD
sets flag.
DSP DATA
D012
Lower
seven
bits are
data
output,
high
order
bit is
"display
ready"
input
(1
equals
ready,
equals
busy)
DSP
Control
Reg.
D013
8-