Apple Lisa - Page 55

Confidential
BR
BG In/
BG Out/
BGACK/
LDMA/
RESET/
+SSIDBY
Lisa Hardware Reference Manual
Bus Request indicates to the 68000 that another
device wishes to take control of the bus.
The 68000 issues a Bus Grant after the DMA device
has been given control of the bus. If no higher
priority device controls the bus and the present
I/O card has asserted Bus Request, the card can
take control of the bus when the Bus Grant signal
is asserted.
The Bus Grant signal is propogated to the lower
priority devices when the current device is not
using the bus.
Bus Grant Acknowledge is produced by the I/O
device when it assumes control of the bus. It
is asserted until that device is finished with
the bus.
Load Direct Memory Access is used to load the
DMA high address latch. Since the expansion
slot has only S6 pins, the high 8 address lines
cannot be sent to memory directly. Instead,
a latch is provided on the CPU board to hold
these 8 bits. !he latch is loaded with the
contents of the low 8 data bits (BDO - BD7)
when there i~ a rising edge on the LDMA/
signal. LDMA/ is pulled up on the CPU board.
The DMA device must load this register each
time it receives control of the bus, before
any DMA cycles occur.
The CPU Clock is the 5 MHz signal that drives the
68000. It can be used as a general purpose clock,
or to control timing during the DMA transfer.
RESET/ tells the I/O device to return to its
power-on state. RESET/ is asserted by the CPU
when the power is turned on, and when the
RESET instruction is executed. When the power
is off, this line can be pulled low to turn
it back on by using the soft-on feature.
This signal provides a +5 volt power supply to
those devices on the I/O board which need to be
powered on whenever
the system is turned on.
The system clock/calendar circuitry is powered
by
this supply. When the normal +5 volt supply
is operating, no current should be drawn from
+5SIDBY. The maximum current that can be drawn
from
this supply is 50 ma per expansion board.
Page 55
7-Jul-8l