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ECO No. DESCRIPTION OF CHANGE
J:\PROJECTS\A9 CD\L816PB DAC PCB\Circuits & PCB\Issue 5\L816c1 5.DDB - Documents\L816c1 .p j
A & R Cambridge Ltd.
Pembroke Avenue
Denny Industrial Centre
Waterbeach
Cambridge CB5 9PB
Alpha 9 CD DAC PCB Top
Circuit Diagram
L816CT
SJB
15-Oct-1999
INITIALS
Date Printed
1 9Sheet of
Notes:
VCCD
DGND
CCLK
DOR
DOL
WCKO
BCKO
WR
DSP
SER_CLK
SER_DIN
SER_CH
D[0. 23]
SEL[0. 2]
RDYO
SRD
SCK
INTR
A[0..15]
L[0..15]
R[0..15]
CLK
PRGM
M0
M2
DONE
MODE0
MODE1
LDC
SER_CH2
AA[0..15]
A/D
NMODE
PMODE
MUTE
HDCD
FPGA
L816C2_5 SCH
VCCD
DGND
A[0..15]
ROM_ENABLE
CLK17M
PCAP
XRST
INTR
LDC
D[0..23]
WR
SRD
SCK
SER_CH
PRGM
CCLK
SCO
SER_CH2
DEEMPH
MUTE
DSP
L816C3_5 SCH
VCC
28
GND
14
OE/VPP
22
CE
20
A0
10
A1
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
3
A8
25
A9
24
A10
21
A11
23
A12
2
A13
26
A14
27
A15
1
D0
11
D1
12
D2
13
D3
15
D4
16
D5
17
D6
18
D7
19
U31
27C512
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D[0..7]
A[0..15]
A[0..15]
D[0. 23]
L[0..15]
R[0..15]
SEL[0..2]
CLK17M
L[0..15]
SEL[0..2]
R[0..15]
RDY
VPROT
AA[0..15]
PMODE
NMODE
A/D
MUTERLY
ASIC DAC
L816C4_5 SCH
1
2
3
U1A
74HC00 SM
4
5
6
U1B
74HC00 SM
8
9
10
U1C
74HC00 SM
11
12
13
U1D
74HC00 SM
DIN
1
BCKI
2
XTIM
3
DITH
4
GAIN
5
XTI
6
VDD1
7
VSS1
8
PROG
9
OSIZ0/MS1
10
OSIZ1/MS2
11
-COB/MS3
12
JUST/MS4
13
BCPL/-MEN
14
SMUTE
15
DEEMPH
16
HMUTE
17
FSEL
18
SCAL
19
DG
20
VSS2
21
VDD2
22
DOR
23
DOL
24
WCKO
25
BCKO
26
HDCD
27
LRCI
28
U16
PMD-100 HDCD
GO
GAIN
POWER SUPPLY
L816C7_5 SCH
R145
15K SM
R162
15K SM
DONE
INTR
SCK
SRD
R91
220R MF
VCCD
VCCD
CLKDAC
CLK17M
R9
100K SM
VCCD
R3
0R0 SM
*
*
R143
0R0 SM
R144
0R0 SM
DONE
*
**
C146
10N SM
VCCD
INTR
LDC
SRD
SCK
R163
100K SM
C128
330P PPS
VCCD
CLK17M
SER_CH
VDD
14
GND
7
U1E
74HC00 SM
C110
10N SM
+5VCLK
Q25
BC849B
R114
100K SM
R23
2K2 SM
R8
4K7 SM
Q1
BC849B
D3
BAS16W SM
RLY_GND
RLYPWR
RA0
XRST
Power ON/OFF MUTE relay
* Fit to HDCD version only
** Fit to DSP version only
R13
100K SM
VCCD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SK3
FFC32V
CLKMECH
SER_CLK
SER_DIN
SER_CH
HDCDLED
XRST
DEEMPH
RA0
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
MUTE
MUTE
DEEMPH
RB7
HDCDLED
RB0
RB6
CLK17M
+
C96
100U EL
C88
10N SM
VCCD
L7
33UH SM
*
R82
1K0 SM
R105
1K0 SM
RB[0..7]
R106
10K SM
R117
1K0 SM
R87
1K0 SM
R85
10K SM
VCCD VCCD
RB4
RB5
***
DSP HDCD
PCB ID
**
**
*
*
* *
*
From FPGA
To DSP
PCAP
GO
ROM_ENABLE
M2
M0
R28
0R0 SM
DSP
RDYO
RDY
BCKO
WCKO
DOL
DOR
MUTERLY
CLK17M
CLKDAC
CLKMECH
XRST
GO
CLOCK
L816C8_5 SCH
CLKDAC
CLKMECH
CLK17M
CLKDAC
CLKMECH
SER_CLK
SER_DIN
SER_CH
MUTE
XRST
DEEMPH
RA0
RB7
RB6
RB5
RB4
RB0
RB1
RB2
RB3
HDCDLED
DGND
C159
10N SM
THL1
FIXING HOLE
THL2
FIXING HOLE
THL3
FIXING HOLE
THL9
FIXING HOLE
THL8
FIXING HOLE
THL7
FIXING HOLE
Photo Strip
PS
PHOTO_STRIP
S J B
SJB
SJB
LDC
R12
100K SM
VCCD
XRST
GO
GO
D11
BAS16W SM
**
**
FD_1
FIDUCIAL
FD_2
FIDUCIAL
RLY1C
RLY 51SB12T
CLK17M
BKin
LRin
D in
DIout
LRoutBKout
RE-LATCH
L816C9_5 SCH
CLK17M
VCCD
1
2
4
3 5
U21
74AHC1G00 SM
VPROT
PCB
L816PB
SER_CH2
AA[0..15]
SER_CH2
DEEMPH
MUTE
MUTE
HDCD
HDCD
R14
470R SM
CLK17M
C8
10N SM
Clock Terminator
C119
10N SM
R122
470R SM
L11
10UH SM
R111
10R SM
THL6
TOOLING
THL4
TOOLING
VHDCD
R110
0R0 SM
R4
0R0 SM
GO
*
**
Q18
BC849B
R74
100K SM
GAIN
GAIN
R81
0R0 SM
1
+
C147
1U0 EL
Runout Sheet Program
Kit mask for DSP
version : DSP
Kit mask for HDCD
version : HDCD
THL5
FIXING HOLE
Paper Marker
A3 Vertical
DD1
DD_A3V
Detail
Drilling
DD2
DRILL_DWG
FD_3
FIDUCIAL
FD_4
FIDUCIAL
FD_5
FIDUCIAL
FD_6
FIDUCIAL
FD_7
FIDUCIAL
BARCODE LABEL
BARCD
BARCODE
* **
R166
4K7 SM
+
C163
220U EL
R167
15K SM
1st Issue
21-APR-98
SJB
98_1020
2
Update Box
UDB
UPDATE_BOX
FR4, 1 OZ Cu
PCB MATERIAL
MULTI LAYER
DD3
FR4_MULTI
U16 Configured in stand-alone mode
13-May-98
SJB
98_1022
5NO CHANGE ON THIS SHEET
14-10-99
WAF
99_1072
3
C170, C171 added for spike suppression
21-Sept-98
SJB
98_1058
4No Change on this sheet
02-Nov-98
LJW
98_1067
C170
10N SM
C171
10N SM
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