ARM MPS3 User Manual

CB_CFGnRST
The reset signal for the serial interface of the Serial Configuration Controller (SCC).
CPUWAIT
Core register that is used to release processor core or cores from reset.
Reset sequence
The following figure shows the MPS3 board reset and powerup timing cycle including board
configuration.
MCC
reset
MCC
config
Power
ON
Board
and
FPGA
config
(inc
FPGA
PLLs)
SCC
config
MCC
reset
PBON/
User ON
CB_VRAMP
FPGA_nRST
CB_CFGnRST
CB_nPOR
CB_nRST
CPUWAIT
(if supported)
nSRST
Subsystem
reset.
Release
logic
reset.
Release
CPU
reset
Release
processor
wait
Processor
boot
System
running
Warm
reset
Pre-load
memory
Figure 2-5 MPS3 board reset and configuration timing
Related information
1.3 Location of components on the MPS3 board on page 1-15
2 Hardware description
2.4 Reset, powerup, and configuration
100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights
reserved.
2-26
Non-Confidential

ARM MPS3 Specifications

General

Brand	ARM
Model	MPS3
Category	Motherboard
Language	English