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ARM MPS3

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SCC
reset
Write
address
CFGDATA
CFGLOAD
CFGWnR
Load
address
and data
Write
data
CB_CFGnRST
CFGCLK
A11 A10 A0 D31
D30
D0
Figure 2-8 Serial Configuration Controller interface write cycle timing
2 Hardware description
2.6 Serial Configuration Controller interface
100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights
reserved.
2-29
Non-Confidential

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