ARP Omni-2 - Synthesizer Board; Voltage Controlled Filter; ADSR Gating; ADSR

= VOLUME/MIX AMPLIFIER
(Refer to Synthesizer Control Board Schematic.)
The Master Volume Control (25А) is used to set the
output level of Strings, Synthesizer and Main Output.
Z5A-1 provides a O to -10V control voltage,
depending on the position of R22, Master Volume
Control Slider, The source of the negative control
voltage is from a (+10V) voltage divider found on the
Bass Board (at J15-4) which supplies Z5A via R37,
100K resistor. The voltage divider can be interrupted
if the volume pedal (commonly called Filter Foot
Pedal) is connected. The result is a variable voltage
source supplied to 25А, It should be noted that the
Volume/Mix control does not affect the level of the
Bass Voice Output.
R23 (Mix Control) attenuates the level of the Strings
ог Synthesizer before it enters the Main Output Mixer
(see Bass Board schematic).
3.4.5 SYNTHESIZER VOICE SELECTION
(Refer to Synthesizer Control Board Schematic.)
The pitch range push buttons, 4" and 8" Synthesizer
route the audio through Z1 to the VCF input on the
Synthesizer Control Board”. CRS and 086 disable
the audio output of the first 20 notes of the
polyphonic tone gates (TDA470's) when the 8° and
16" Bass voice pitch ranges are selected,
"The 8" and 16" Bass voices are routed to the Bass
УСЕ via P15:2 and P15-3 respectively,
3.5 Synthesizer Board
GENERAL: The Synthesizer Board contains the
Voltage Controlled Filter, ADSR Envelope Genera-
tor, ADSR Gating and Gate and Trigger Output
Processing circuits.
3.5.1 VOLTAGE CONTROLLED FILTER
(Refer to Synthesizer Board Schematic.)
The two pitch ranges, 4' and 8" Polyphonic are
summed and voiced on the audio input of the МСЕ
(pin 1, M1). M1 is а 4075 Low Pass Voltage Control-
led Filter. It has a cutoff of 24 dB/Octave and has
а manually variable Q (resonance). The filter
accepts negative control voltages (1 volts/octave)
on pin 4 to control the filter cutoff point. 218 sums
and inverts external voltages which control the VCF
R22, the CVR (Control Voltage Reset) trimmer,
prevents control voltages from affecting the audio
output (pin 10). The output of the VCF is routed
to the Synthesizer УСА via J12, pin 5.
3.5.2 ADSR GATING
(Refer to Synthesizer Board Schematic.)
To "start" the ADSR Envelope Generator, the output.
of Z3A must change from o volts to -15 volts
(Logic 1 to Logic 0). Two signals must be sent to the
ADSR Gating to set up this condition: the Upper
Gate and Pulse Drive, The Upper Gate (212-11) is 15
volts when no keys are depressed and goes to ground
(Logic 0) when a key is selected. It is called the
Upper Gate because if the B' or 16’ Bass Voice i
selected, no change will appear on J12-3 when lower
keys (1-20) are depressed. This means that for the
above mentioned condition, the lower keys will not
initiate the ADSR. When Z4B-4 goes to Logic 0, the
flop made up of 240 and 240 will b
ted—causing Z3A-3 to go to Logic O (-15 volts). This
starts the ADSR cycle. Z3A-3 will remain at Logic O
as long as a key is held.
The Pulse Drive is used to interrupt the logic level of
Z3A—which will restart the ADSR. The Pulse Drive
occurs every time another key is depressed (multiple
triggering). But if the Single/Multiple input (J12-14)
is +15 volts, the Pulse Drive input will have no effect
оп the condition of Z3A. Therefore, the ADSR will
only be initiated on the first key depression,
3.5.3 ADSR
The ADSR Envelope Generator circuit provides a
negative going DC voltage to control the VCF cutoff
and the УСА.
ATTACK: When the output of Z3A changes from
high to low, -15 volts is applied through CR2 and
R46 to the noninverting input of follower Z2.
During the attack mode, 04 is off and RAS is discon-
nected from ground, 22 directly follows the voltage
оп pin З and applies -15 volts through CR6, R52 to
charge integrating capacitor C13 down.
DECAY AND SUSTAIN: 21А is a buffer amplifier
following the voltage on capacitor 013, When the
output of ADSR voltage approaches -10V, Q2 begins
to turn off and R36 lowers the voltage on pin 13 of
230. Z3C and 230 is a bistable latch. When pin 13
falls below the threshold of the nand gate (about
77.8 volts) the output of 230 changes from high to
low applying -15 volts from pin 10 of Z3 through
CRA, R38 and САЗ thus holding Q2 off. 04 now
turns on and the voltage divider consisting of R45
and R46 establishes the Sustain Level. CR is now
reverse biased and capacitor C13 discharges through
R51 and CRS to the level at Z2 pin 3.
RELEASE: When the gate voltage is removed, 238
goes low which turns on Q6. The remaining voltage