ASROCK AM1H-ITX - Dram Timing Control

AM1H-ITX
37
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DRAM Timing Control
Power Down Enable
Use this item to enable or disable DDR power down mode.
Bank Interleaving
Interleaving allows memory accesses to be spread out over banks on the same node, or
accross nodes, decreasing access contention.
CAS# Latency (tCL)
e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
e number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.