ASROCK H97M-ITX/ac - Page 65

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CAS Write Latency (tCWL)
Congure CAS Write Latency.
tREFI
Congure refresh cycles at an average periodic interval.
tCKE
Congure the period of time the DDR3 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD
Congure between module read to read delay.
tRDRDDR
Congure between module read to read delay from dierent ranks.
tRDRDDD
Use this to change DRAM tRWSR Auto/Manual settings. e default is [Auto].
tWRRD
Congure between module write to read delay.
tWRRDDR
Congure between module write to read delay from dierent ranks.
tWRRDDD
Use this to change DRAM tRRSR Auto/Manual settings. e default is [Auto].
Congure between module write to read delay from dierent DIMMs.
tWRWR
Congure between module write to write delay.
tWRWRDR
Congure between module write to write delay from dierent ranks.
tWRWRDD
Congure between module write to write delay from dierent DIMMs.
tRDWR
Congure between module read to write delay.