ASROCK H97M-ITX/ac - Page 66

H97M-ITX/ac
61
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tRDWRDR
Congure between module read to write delay from dierent ranks.
tRDWRDD
Congure between module read to write delay from dierent DIMMs.
RTL (CHA)
Congure round trip latency for channel A.
RTL (CHB)
Congure round trip latency for channel B.
IO-L (CHA)
Congure IO latency for channel A.
IO-L (CHB)
Congure IO latency for channel B.
ODT WR (CHA)
Congure the memory on die termination resistors' WR for channel A.
ODT WR (CHB)
Congure the memory on die termination resistors' WR for channel B.
ODT NOM (CHA)
Use this to change ODT (CHA) Auto/Manual settings. e default is [Auto].
ODT NOM (CHB)
Use this to change ODT (CHB) Auto/Manual settings. e default is [Auto].
Command Tri State
Enable for DRAM power saving.
MRC Fast Boot
Enable Memory Fast Boot to skip DRAM memory training for booting faster.
DIMM Exit Mode
Select Slow Exit to reduce power consumption, or Fast Exit for better performance.