APPENDIX F
register, and an 8-bit interval counter, whose value decreî™…
ments by one at every impulse. When the interval counter
timer reaches 0, the value of the data register is loaded into
the counter, and an interrupt will be generated if enabled.
The source of the impulse that causes the counter to decî™…
rement may be a clock pulse (Delay mode), or an external
signal (Event Count mode). There is also a combined mode
(Pulse Length mode), in which the clock is turned on and off
by the external signal.
The control registers use bits 0-3 to determine the mode
in which the timers will function. The possible combinations
are detailed in Table F-3.
Table F-3. Timer A and B Register Values and Timer Modes
Register Value Timer Mode
0 Timer off
1 Delay mode, clock divided by 4
2 Delay mode, clock divided by 10
3 Delay mode, clock divided by 16
4 Delay mode, clock divided by 50
5 Delay mode, clock divided by 64
6 Delay mode, clock divided by 100
7 Delay mode, dock divided by 200
8 Event Count Mode
9 Pulse Length mode, clock divided by 4
10 Pulse Length mode, clock divided by 10
11 Pulse Length mode, clock divided by 16
12 Pulse Length mode, clock divided by 50
13 Pulse Length mode, clock divided by 64
14 Pulse Length mode, clock divided by 100
15 Pulse Length mode, clock divided by 200
Bit four (value of 16) can be used to force a timer reset.
Register 15. Timers C and D Control Register (TCDCR).
Since Timers C and D only run in Delay mode, only one byte
is needed for their control register. The upper nibble controls
Timers C, while the lower nibble controls timer D, as shown
in Table F-4.
Table F-4. Control Register Values for Timers C and D
Timer C Timer D
Value Value Timer Mode
0 0 Timer off
16 1 Delay mode, clock divided by 4
32 2 Delay mode, clock divided by 10
304
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