Atmel AT89C2051 - User Manual

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Features

• Compatible with MCS

-51Products

• 2K Bytes of Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• 2.7V to 6V Operating Range

• Fully Static Operation: 0 Hz to 24 MHz

• Two-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 15 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial UART Channel

• Direct LED Drive Outputs

• On-chip Analog Comparator

• Low-power Idle and Power-down Modes

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with

2K bytes of Flash programmable and erasable read-only memory (PEROM). The

device is manufactured using Atmel’s high-density nonvolatile memory technology

and is compatible with the industry-standard MCS-51 instruction set. By combining a

versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a power-

ful microcomputer which provides a highly-flexible and cost-effective solution to many

embedded control applications.

The AT89C2051 provides the following standard features: 2K bytes of Flash, 128

bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt

architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator

and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-

tion down to zero frequency and supports two software selectable power saving

modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial

port and interrupt system to continue functioning. The power-down mode saves the

RAM contents but freezes the oscillator disabling all other chip functions until the next

hardware reset.

8-bit

Microcontroller

with 2K Bytes

Flash

AT89C2051

0368G–MICRO–6/05

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The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer, part of Atmel's family of microcontrollers. It is compatible with the MCS®-51 instruction set, offering a versatile and cost-effective solution for embedded control applications.

Function Description:

The device integrates a powerful 8-bit CPU with 2K bytes of Flash programmable and erasable read-only memory (PEROM). This Flash memory has an endurance of 1,000 write/erase cycles. It operates within a 2.7V to 6V range and supports fully static operation from 0 Hz to 24 MHz. Key features include a two-level program memory lock, 128 x 8-bit internal RAM, and 15 programmable I/O lines. For timing, it has two 16-bit timer/counters and six interrupt sources. Communication is handled by a programmable serial UART channel. The device also offers direct LED drive outputs, an on-chip analog comparator, and integrated oscillator and clock circuitry. It supports two software-selectable power-saving modes: Idle Mode and Power-down Mode. The Idle Mode stops the CPU while keeping RAM, timer/counters, serial port, and interrupt system active. The Power-down Mode saves RAM contents but freezes the oscillator, disabling other chip functions until a hardware reset. The device is available in green (Pb/Halide-free) packaging options.

Important Technical Specifications:

Memory: 2K bytes Flash PEROM (1,000 write/erase cycles endurance), 128 bytes internal RAM.
Operating Voltage: 2.7V to 6V.
Operating Frequency: 0 Hz to 24 MHz (fully static operation).
I/O Lines: 15 programmable bi-directional I/O lines (Port 1 and Port 3).
- Port 1 pins P1.2 to P1.7 have internal pull-ups. P1.0 and P1.1 require external pull-ups and also serve as inputs for the on-chip analog comparator (AIN0 and AIN1). Port 1 output buffers can sink 20 mA.
- Port 3 pins P3.0 to P3.5 and P3.7 are bi-directional with internal pull-ups. P3.6 is hard-wired as an input to the comparator output. Port 3 output buffers can sink 20 mA.
Timer/Counters: Two 16-bit timer/counters.
Interrupts: Six interrupt sources, five-vector two-level interrupt architecture.
Serial Communication: Full duplex serial port (UART).
Analog Features: On-chip precision analog comparator.
Power Consumption (Typical, 85°C):
- Active Mode (12 MHz, Vcc=6V/3V): 15/5.5 mA.
- Idle Mode (12 MHz, Vcc=6V/3V, P1.0 & P1.1 = 0V or Vcc): 5/1 mA.
- Power-down Mode (Vcc=6V, P1.0 & P1.1 = 0V or Vcc): 100 µA.
- Power-down Mode (Vcc=3V, P1.0 & P1.1 = 0V or Vcc): 20 µA.
Pin Capacitance: 10 pF (Test Freq. = 1 MHz, TA = 25°C).
Reset: RST input, all I/O pins reset to 1s when RST goes high. Requires holding RST high for two machine cycles while the oscillator runs.
Packaging: Available in 20-lead PDIP (20P3) and 20-lead SOIC (20S) packages.

Usage Features:

Programming: The 2K bytes of Flash PEROM are programmable one byte at a time. To reprogram any non-blank byte, the entire memory array must be erased electrically.
- Programming Algorithm: Involves a power-up sequence (apply Vcc/GND, set RST/XTAL1 to GND), setting RST and P3.2 to "H", and applying logic levels to P3.3, P3.4, P3.5, P3.7 to select programming operations. Data for code bytes is applied to P1.0-P1.7. RST is raised to 12V for programming, and P3.2 is pulsed to program a byte (typically 1.2 ms). XTAL1 is pulsed to advance the internal address counter.
- Data Polling: Features Data Polling on P1.7 to indicate the end of a write cycle.
- Ready/Busy: P3.1 indicates BUSY (low) during programming and READY (high) when done.
- Chip Erase: The entire PEROM array and lock bits are erased electrically by holding P3.2 low for 10 ms.
- Signature Bytes: Can be read to identify the manufacturer (1EH for Atmel) and device (21H for AT89C2051).
Oscillator: Can be configured with a quartz crystal or ceramic resonator (Figure 5-1). For external clock sources, XTAL2 should be left unconnected, and XTAL1 driven by the external clock (Figure 5-2).
Special Function Registers (SFRs): A map of the on-chip memory area for SFRs is provided, with reset values. Users should avoid writing 1s to unlisted locations.
Instruction Set Compatibility: Fully compatible with MCS-51 instruction set. However, users must ensure that jump/branch destination addresses fall within the 2K program memory space (00H to 7FFH). External data memory access (MOVX instructions) and external program memory execution are not supported.
Power Management:
- Idle Mode: CPU stops, peripherals remain active. Terminated by enabled interrupt or hardware reset. P1.0 and P1.1 should be set to "0" (no external pull-ups) or "1" (external pull-ups).
- Power-down Mode: Oscillator stops, RAM and SFRs retain values. Terminated only by hardware reset. P1.0 and P1.1 should be set to "0" (no external pull-ups) or "1" (external pull-ups).
Program Memory Lock Bits: Two lock bits (LB1, LB2) offer protection features:
- No lock features (LB1=U, LB2=U).
- Further programming of Flash disabled (LB1=P, LB2=U).
- Programming and verification disabled (LB1=P, LB2=P). Lock bits can only be erased with a Chip Erase operation.

Maintenance Features:

Verification: Programmed data can be verified by reading output data at Port 1 pins after programming. Lock bits cannot be directly verified but their features can be observed.
Reset Functionality: A hardware reset ensures a defined state for the device, resetting I/O pins to 1s and the internal PEROM address counter to 000H.
Reliability: Atmel provides information on absolute maximum ratings and DC characteristics to guide proper usage and ensure device reliability. Exceeding these ratings can cause permanent damage.