78 APx PDM I/O Module for B Series: Specifications
PDM
Timing Characteristics
PDM TRANSMITTER
t
CLKTX
Clock period (master or slave
mode)
41 7813 ns
t
H
Data hold time 20 ns
t
SU
Data setup time
t
CLKTX
/ 2-30
ns
Logic Level = 0.8 V
t
CO
Clock to out 58 ns
t
R
Rise Time 18 ns
t
F
Fall Time 16 ns
r
OUT
Output Impedance 450 ohms
f
CLK
max
Maximum Clock Frequency 3.072 MHz
Logic Level = 1.0 V
t
CO
Clock to out 32 ns
t
R
Rise Time 10 ns
t
F
Fall Time 7.7 ns
r
OUT
Output Impedance 225 ohms
f
CLK
max
Maximum Clock Frequency 6.144 MHz
Logic Level = 1.5 V
t
CO
Clock to out 18 ns
t
R
Rise Time 5.2 ns
t
F
Fall Time 3.8 ns
r
OUT
Output Impedance 85 ohms
f
CLK
max
Maximum Clock Frequency 12.28 MHz
Parameter Symbol Test Conditions Min Typ Max Unit