Digital Counter / Timer / Tach User Manual, 1st Ed.
4-53
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Timer + Counter Mixed Mode
In Timer + Counter Mixed Mode, timer period setting value SV1 controls Output 1 and counter setting value SV2
controls Output 2. Output 1(Timer) will turn ON momentarily for the time set in the output pulse width parameter
(
tout1
) or will be maintained ON (
tout1
set to 0.00). Output 2 (Counter) will turn ON momentarily for the
time set in the output pulse width parameter (
tout2
) or will be maintained ON depending on the output mode
selected.
CTT Timer + Counter Mixed Mode Functions
Timer Mode - Power On Delay HOLD (PondH)
Counter Input Mode -Up (
up
)
Timer Mode - Power On Delay HOLD (
PondH
)
When power is applied to the CTT, the timing period setting value SV1
will begin timing up or down based on parameter (
t modE
). At the end
of the timing period Output 1 will turn ON momentarily for the time set
in the output pulse width parameter (tout1) or will be maintained ON if
the output pulse width parameter (tout1) is set to 0.00.
The leading edge of a “reset” input signal at RST1 will turn OFF Output
1, reset the timing period and prohibit the start of a new timing period.
The “reset” signal minimum pulse width is set by reset pulse width param-
eter (
rtSr
).
The leading edge of an “pause” input signal at GATE will pause the
timing period after it has been started. The timing period will continue
after the trailing edge of the “pause” (Gate) signal.
When power is removed, Output 1 will turn OFF. The last state of the
output and the last value of the current timing period will be “stored”
when power is removed. When power is reapplied the output will return
to its last state and timing will resume from the last value of the timing
period.
Counter Input Mode:
Mode F (
F
)
When the count present value PV counts up to the count
setting value SV2 Output 2 will turn ON. The count PV will
continue to increment with each input signal.
The leading edge of a “reset” input signal at RST1 will turn
Output 2 OFF, reset the count PV to 0, and prohibit an input
signal from incrementing the count PV. The trailing edge of the
“reset” signal at RST1 enables counting to begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
).
Counter Output Modes:
Counter Input Mode - Counting Up (
UP
)
Each leading edge of the input signal at CP1 will increment the count present value PV by 1.
Timer+Counter Mixed Mode
999999
RESET
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