Digital Counter / Timer / Tach User Manual, 1st Ed.
2-49
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999999
SV2
SV1
PV
OUT2
OUT1
Stage 2
Input Mode UdB
0
Mode T(
t
)
When the count present value PV is less than the count setting value SV1, Output 1 will be ON and will turn OFF
when the count PV counts up to the count SV1. When the count PV counts down to the count SV1 Output 1 turn
ON. . When the count PV counts up to the count SV2 Output 2 will turn ON. When the count PV counts down
to the count SV2 Output 2 will turn OFF. The count PV will continue to increment or decrement with each input
signal.
The leading edge of a “reset” input signal at RST1 will turn OFF both outputs, reset the count PV to 0, and prohibit
an input signal from incrementing or decrementing the count PV. The trailing edge of the “reset” signal at RST1
enables counting to begin.
The “reset” signal minimum pulse width is set by reset pulse width parameter (
rtSr
) or DIP Switch 8.
Stage 2
Input Mode UdB
999999
SV2
SV1
PV
OUT2
OUT1
0
Mode D (
d
)
When the count present value PV counts up or counts down to the count setting value SV1 Output 1 will turn ON
momentarily for the time set in the output pulse width parameter (
tout1
). When the count present value PV counts
up or counts down to the count SV2 Output 2 will turn ON momentarily for the time set in the output pulse width
parameter (
tout2
). The count PV will continue to increment or decrement with each input signal.
The leading edge of a “reset” input signal at RST1 will turn OFF both outputs, reset the count PV to 0, and prohibit
an input signal from incrementing or decrementing the count PV. The trailing edge of the “reset” signal at RST1
enables counting to begin.
The “reset” signal minimum pulse width is set by reset pulse width parameter (
rtSr
) or DIP Switch 8.