EtherCAT communication EL6731-00x0
EL6731 139Version: 2.8
configured DP slaves have been dealt with, the EtherCAT input data is updated and the DP cycle is finished.
If the next SM2 (SM3) event is received before the DP cycle is completed, the Cycle Exceed counter
(0x1C32:0B or 0x1C33:0B) is incremented and one DP cycle is skipped.
SYNC0-synchronous
The DP cycle is started by the SM2 (SM3) event. The sending of the first telegram is delayed until the
SYNC0 event occurs, so that the sending of the Global Control telegram takes place with a jitter of maximum
500 ns. The remainder of the DP cycle sequence corresponds to that in the case of synchronization without
Distributed Clocks.
Transmission of the process data with LRW telegram (Separate Input Update = FALSE)
The illustration below shows the sequence of the DP cycle and the meaning of the Sync Manager
parameters if the DP cycle is controlled with Distributed Clocks via SM and SYNC0 event.
Fig.132: DP cycle with distributed clocks and control via SM and SYNC0 event
Transmission of the output data with LWR telegram and the input data with LRD telegram (Separate
Input Update = TRUE, Task Cycle Time = Base Time)
If EtherCAT outputs and inputs are transmitted with separate telegrams, so that the inputs are as up to date
as possible (click on Separate Input Update for the associated TwinCAT task in the TwinCAT System
Manager), there is less room for the DP cycle. If the Task Cycle Time (= EtherCAT Master Cycle Time) is
equal to the TwinCAT Realtime Base Time, the LRD telegram, with which the inputs are read in as late as
possible, is sent in accordance with the set CPU limit.
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