ES6688A Pin Description
Names Pin Numbers I/
O Definitions
VD3
3
1, 10, 19, 35, 44,
53, 62, 79, 96, 126,
18
5
P I/O power supply.
VID_XI 2 I Crystal input.
VID_XO 3 O Crystal output
.
CLK 4 I System clock.
DMA[11:0] 5:8 11:17, 20 O DRAM address bus.
VS33
9, 18, 34, 43, 52,
61, 78, 95, 119, 127,
186, 20
8
G Ground for I/O power supply
.
DCAS# 21 O DRAM column address strobe (active-low).
DCS[1:0]# 22, 23 O DRAM chip
select (active-low).
DRAS[2:0]# 24, 25, 28 O DRAM row address strobe (active-low)
.
VSS 26, 70, 86, 137, 197 G Ground for core power supply.
VDD 27, 71, 87, 138, 198 P Core power supply.
DSCK_EN
29
O DRAM clock enable output.
DOE# O DRAM output enable (active-low)
.
DWE# 30 O DRAM write enable (active-low).
DB[15:0] 31:33, 36:42, 45:50 I/O DRAM
data bus.
DSCK 51 O Output clock to DRAM.
DQM 54 O Data input/output mask
.
LA[21:0]
55:60, 63:69, 72:77,
80:8
2
O RISC port address bus
.
LCS0
#
83
O RISC port chip select (active-low).
PIXOUT_CLK O CCIR656 output pixel clock.
LCS[3:1]# 84, 85, 88 O RISC port chip select (active-low).
LWRLL# 89 O RISC port low-byte write enable (active-low).
LOE# 90 O RISC port output enable (active-low).
LD[7:0] 91:94, 97:100 I/O RISC port data
bus; (5V tolerant input).
RSD 101 I Audio receive serial data; (5V tolerant input).
RBCK 102 I Audio receive bit clock; (5V tolerant input).
RWS 103 I Audio receive frame sync; (5V tolerant input).
VD33_PL 104 P Power for PLL blocks
.
VS33_PL 105 G Ground for PLL blocks.
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