Bradley 233 - Page 18

4.1.1 Amplifier
Fig. 2 shows that a gate has gain when its input is near to -1.3V,but when the outputs reach
the logic levels they are limited and the gain is zero.
vcc (ov)
OUT O-
IN 1 O-
IN 2 O-
1_.
VBB
-O OUT
J
VEC (-6V)
FIG.1 E.C.L. LOGIC
IN 1
IN2
&
OUT
• OUT
THRESHOLD
-1-3
V IN
OUT
OUT J
-0-9V HIGH STATE
-1-3V
-1 ■ 9V LOW STATE
V OUT
fig. 2 LOGIC LEVELS
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